xref: /linux/Documentation/devicetree/bindings/pinctrl/renesas,rza2-pinctrl.yaml (revision 06d07429858317ded2db7986113a9e0129cd599b)
14d0e6267SGeert Uytterhoeven# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
24d0e6267SGeert Uytterhoeven%YAML 1.2
34d0e6267SGeert Uytterhoeven---
44d0e6267SGeert Uytterhoeven$id: http://devicetree.org/schemas/pinctrl/renesas,rza2-pinctrl.yaml#
54d0e6267SGeert Uytterhoeven$schema: http://devicetree.org/meta-schemas/core.yaml#
64d0e6267SGeert Uytterhoeven
74d0e6267SGeert Uytterhoeventitle: Renesas RZ/A2 combined Pin and GPIO controller
84d0e6267SGeert Uytterhoeven
94d0e6267SGeert Uytterhoevenmaintainers:
104d0e6267SGeert Uytterhoeven  - Chris Brandt <chris.brandt@renesas.com>
114d0e6267SGeert Uytterhoeven  - Geert Uytterhoeven <geert+renesas@glider.be>
124d0e6267SGeert Uytterhoeven
134d0e6267SGeert Uytterhoevendescription:
144d0e6267SGeert Uytterhoeven  The Renesas SoCs of the RZ/A2 series feature a combined Pin and GPIO
154d0e6267SGeert Uytterhoeven  controller.
164d0e6267SGeert Uytterhoeven  Pin multiplexing and GPIO configuration is performed on a per-pin basis.
174d0e6267SGeert Uytterhoeven  Each port features up to 8 pins, each of them configurable for GPIO function
184d0e6267SGeert Uytterhoeven  (port mode) or in alternate function mode.
194d0e6267SGeert Uytterhoeven  Up to 8 different alternate function modes exist for each single pin.
204d0e6267SGeert Uytterhoeven
214d0e6267SGeert Uytterhoevenproperties:
224d0e6267SGeert Uytterhoeven  compatible:
23*dc99d4c8SRob Herring    const: renesas,r7s9210-pinctrl # RZ/A2M
244d0e6267SGeert Uytterhoeven
254d0e6267SGeert Uytterhoeven  reg:
264d0e6267SGeert Uytterhoeven    maxItems: 1
274d0e6267SGeert Uytterhoeven
284d0e6267SGeert Uytterhoeven  gpio-controller: true
294d0e6267SGeert Uytterhoeven
304d0e6267SGeert Uytterhoeven  '#gpio-cells':
314d0e6267SGeert Uytterhoeven    const: 2
324d0e6267SGeert Uytterhoeven    description:
334d0e6267SGeert Uytterhoeven      The first cell contains the global GPIO port index, constructed using the
344d0e6267SGeert Uytterhoeven      RZA2_PIN() helper macro in r7s9210-pinctrl.h.
354d0e6267SGeert Uytterhoeven      E.g. "RZA2_PIN(PORT6, 0)" for P6_0.
364d0e6267SGeert Uytterhoeven
374d0e6267SGeert Uytterhoeven  gpio-ranges:
384d0e6267SGeert Uytterhoeven    maxItems: 1
394d0e6267SGeert Uytterhoeven
4025990aabSRob HerringadditionalProperties:
414d0e6267SGeert Uytterhoeven  type: object
4225990aabSRob Herring
434d0e6267SGeert Uytterhoeven  allOf:
444d0e6267SGeert Uytterhoeven    - $ref: pincfg-node.yaml#
454d0e6267SGeert Uytterhoeven    - $ref: pinmux-node.yaml#
4625990aabSRob Herring
474d0e6267SGeert Uytterhoeven  description:
484d0e6267SGeert Uytterhoeven    The child nodes of the pin controller designate pins to be used for
494d0e6267SGeert Uytterhoeven    specific peripheral functions or as GPIO.
504d0e6267SGeert Uytterhoeven
514d0e6267SGeert Uytterhoeven    A pin multiplexing sub-node describes how to configure a set of
524d0e6267SGeert Uytterhoeven    (or a single) pin in some desired alternate function mode.
534d0e6267SGeert Uytterhoeven    The values for the pinmux properties are a combination of port name,
544d0e6267SGeert Uytterhoeven    pin number and the desired function index. Use the RZA2_PINMUX macro
554d0e6267SGeert Uytterhoeven    located in include/dt-bindings/pinctrl/r7s9210-pinctrl.h to easily
564d0e6267SGeert Uytterhoeven    define these.
574d0e6267SGeert Uytterhoeven    For assigning GPIO pins, use the macro RZA2_PIN also in
584d0e6267SGeert Uytterhoeven    to express the desired port pin.
594d0e6267SGeert Uytterhoeven
604d0e6267SGeert Uytterhoeven  properties:
614d0e6267SGeert Uytterhoeven    pinmux:
624d0e6267SGeert Uytterhoeven      description:
634d0e6267SGeert Uytterhoeven        Values are constructed from GPIO port number, pin number, and
644d0e6267SGeert Uytterhoeven        alternate function configuration number using the RZA2_PINMUX()
654d0e6267SGeert Uytterhoeven        helper macro in r7s9210-pinctrl.h.
664d0e6267SGeert Uytterhoeven
674d0e6267SGeert Uytterhoeven  required:
684d0e6267SGeert Uytterhoeven    - pinmux
694d0e6267SGeert Uytterhoeven
704d0e6267SGeert Uytterhoeven  additionalProperties: false
714d0e6267SGeert Uytterhoeven
72c09acbc4SRafał MiłeckiallOf:
7349cd1dd1SRob Herring  - $ref: pinctrl.yaml#
74c09acbc4SRafał Miłecki
754d0e6267SGeert Uytterhoevenrequired:
764d0e6267SGeert Uytterhoeven  - compatible
774d0e6267SGeert Uytterhoeven  - reg
784d0e6267SGeert Uytterhoeven  - gpio-controller
794d0e6267SGeert Uytterhoeven  - '#gpio-cells'
804d0e6267SGeert Uytterhoeven  - gpio-ranges
814d0e6267SGeert Uytterhoeven
824d0e6267SGeert Uytterhoevenexamples:
834d0e6267SGeert Uytterhoeven  - |
844d0e6267SGeert Uytterhoeven    #include <dt-bindings/pinctrl/r7s9210-pinctrl.h>
85d4691b7fSGeert Uytterhoeven    pinctrl: pinctrl@fcffe000 {
864d0e6267SGeert Uytterhoeven            compatible = "renesas,r7s9210-pinctrl";
874d0e6267SGeert Uytterhoeven            reg = <0xfcffe000 0x1000>;
884d0e6267SGeert Uytterhoeven
894d0e6267SGeert Uytterhoeven            gpio-controller;
904d0e6267SGeert Uytterhoeven            #gpio-cells = <2>;
914d0e6267SGeert Uytterhoeven            gpio-ranges = <&pinctrl 0 0 176>;
924d0e6267SGeert Uytterhoeven
934d0e6267SGeert Uytterhoeven            /* Serial Console */
944d0e6267SGeert Uytterhoeven            scif4_pins: serial4 {
954d0e6267SGeert Uytterhoeven                    pinmux = <RZA2_PINMUX(PORT9, 0, 4)>, /* TxD4 */
964d0e6267SGeert Uytterhoeven                             <RZA2_PINMUX(PORT9, 1, 4)>; /* RxD4 */
974d0e6267SGeert Uytterhoeven            };
984d0e6267SGeert Uytterhoeven    };
99