xref: /linux/Documentation/devicetree/bindings/pinctrl/realtek,rtd1319d-pinctrl.yaml (revision 0ea5c948cb64bab5bc7a5516774eb8536f05aa0d)
1*bc8d39a5STzuyi Chang# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
2*bc8d39a5STzuyi Chang# Copyright 2023 Realtek Semiconductor Corporation
3*bc8d39a5STzuyi Chang%YAML 1.2
4*bc8d39a5STzuyi Chang---
5*bc8d39a5STzuyi Chang$id: http://devicetree.org/schemas/pinctrl/realtek,rtd1319d-pinctrl.yaml#
6*bc8d39a5STzuyi Chang$schema: http://devicetree.org/meta-schemas/core.yaml#
7*bc8d39a5STzuyi Chang
8*bc8d39a5STzuyi Changtitle: Realtek DHC RTD1319D Pin Controller
9*bc8d39a5STzuyi Chang
10*bc8d39a5STzuyi Changmaintainers:
11*bc8d39a5STzuyi Chang  - TY Chang <tychang@realtek.com>
12*bc8d39a5STzuyi Chang
13*bc8d39a5STzuyi Changdescription:
14*bc8d39a5STzuyi Chang  The Realtek DHC RTD1319D is a high-definition media processor SoC. The
15*bc8d39a5STzuyi Chang  RTD1319D pin controller is used to control pin function, pull up/down
16*bc8d39a5STzuyi Chang  resistor, drive strength, schmitt trigger and power source.
17*bc8d39a5STzuyi Chang
18*bc8d39a5STzuyi Changproperties:
19*bc8d39a5STzuyi Chang  compatible:
20*bc8d39a5STzuyi Chang    const: realtek,rtd1319d-pinctrl
21*bc8d39a5STzuyi Chang
22*bc8d39a5STzuyi Chang  reg:
23*bc8d39a5STzuyi Chang    maxItems: 1
24*bc8d39a5STzuyi Chang
25*bc8d39a5STzuyi ChangpatternProperties:
26*bc8d39a5STzuyi Chang  '-pins$':
27*bc8d39a5STzuyi Chang    type: object
28*bc8d39a5STzuyi Chang    allOf:
29*bc8d39a5STzuyi Chang      - $ref: pincfg-node.yaml#
30*bc8d39a5STzuyi Chang      - $ref: pinmux-node.yaml#
31*bc8d39a5STzuyi Chang
32*bc8d39a5STzuyi Chang    properties:
33*bc8d39a5STzuyi Chang      pins:
34*bc8d39a5STzuyi Chang        items:
35*bc8d39a5STzuyi Chang          enum: [ gpio_0, gpio_1, gpio_2, gpio_3, gpio_4, gpio_5, gpio_6, gpio_7,
36*bc8d39a5STzuyi Chang                  gpio_8, gpio_9, gpio_10, gpio_11, gpio_12, gpio_13, gpio_14,
37*bc8d39a5STzuyi Chang                  gpio_15, gpio_16, gpio_17, gpio_18, gpio_19, gpio_20, gpio_21,
38*bc8d39a5STzuyi Chang                  gpio_22, gpio_23, usb_cc2, gpio_25, gpio_26, gpio_27, gpio_28,
39*bc8d39a5STzuyi Chang                  gpio_29, gpio_30, gpio_31, gpio_32, gpio_33, gpio_34, gpio_35,
40*bc8d39a5STzuyi Chang                  hif_data, hif_en, hif_rdy, hif_clk, gpio_40, gpio_41, gpio_42,
41*bc8d39a5STzuyi Chang                  gpio_43, gpio_44, gpio_45, gpio_46, gpio_47, gpio_48, gpio_49,
42*bc8d39a5STzuyi Chang                  gpio_50, usb_cc1, gpio_52, gpio_53, ir_rx, ur0_rx, ur0_tx,
43*bc8d39a5STzuyi Chang                  gpio_57, gpio_58, gpio_59, gpio_60, gpio_61, gpio_62, gpio_63,
44*bc8d39a5STzuyi Chang                  gpio_64, emmc_rst_n, emmc_dd_sb, emmc_clk, emmc_cmd, emmc_data_0,
45*bc8d39a5STzuyi Chang                  emmc_data_1, emmc_data_2, emmc_data_3, emmc_data_4, emmc_data_5,
46*bc8d39a5STzuyi Chang                  emmc_data_6, emmc_data_7, dummy, gpio_78, gpio_79, gpio_80,
47*bc8d39a5STzuyi Chang                  gpio_81, ur2_loc, gspi_loc, hi_width, sf_en, arm_trace_dbg_en,
48*bc8d39a5STzuyi Chang                  ejtag_aucpu_loc, ejtag_acpu_loc, ejtag_vcpu_loc, ejtag_scpu_loc,
49*bc8d39a5STzuyi Chang                  dmic_loc, ejtag_secpu_loc, vtc_dmic_loc, vtc_tdm_loc, vtc_i2si_loc,
50*bc8d39a5STzuyi Chang                  tdm_ai_loc, ai_loc, spdif_loc, hif_en_loc, sc0_loc, sc1_loc,
51*bc8d39a5STzuyi Chang                  scan_switch, wd_rset, boot_sel, reset_n, testmode ]
52*bc8d39a5STzuyi Chang
53*bc8d39a5STzuyi Chang      function:
54*bc8d39a5STzuyi Chang        enum: [ gpio, nf, emmc, tp0, tp1, sc0, sc0_data0, sc0_data1, sc0_data2,
55*bc8d39a5STzuyi Chang                sc1, sc1_data0, sc1_data1, sc1_data2, ao, gspi_loc0, gspi_loc1,
56*bc8d39a5STzuyi Chang                uart0, uart1, uart2_loc0, uart2_loc1, i2c0, i2c1, i2c3, i2c4,
57*bc8d39a5STzuyi Chang                i2c5, pcie1, sdio, etn_led, etn_phy, spi, pwm0_loc0, pwm0_loc1,
58*bc8d39a5STzuyi Chang                pwm1_loc0, pwm1_loc1, pwm2_loc0, pwm2_loc1, pwm3_loc0, pwm3_loc1,
59*bc8d39a5STzuyi Chang                qam_agc_if0, qam_agc_if1, spdif_optical_loc0, spdif_optical_loc1,
60*bc8d39a5STzuyi Chang                usb_cc1, usb_cc2, vfd, sd, dmic_loc0, dmic_loc1, ai_loc0, ai_loc1,
61*bc8d39a5STzuyi Chang                tdm_ai_loc0, tdm_ai_loc1, hi_loc0, hi_m, vtc_i2so, vtc_i2si_loc0,
62*bc8d39a5STzuyi Chang                vtc_i2si_loc1, vtc_dmic_loc0, vtc_dmic_loc1, vtc_tdm_loc0,
63*bc8d39a5STzuyi Chang                vtc_tdm_loc1, dc_fan, pll_test_loc0, pll_test_loc1, ir_rx,
64*bc8d39a5STzuyi Chang                uart2_disable, gspi_disable, hi_width_disable, hi_width_1bit,
65*bc8d39a5STzuyi Chang                sf_disable, sf_enable, scpu_ejtag_loc0, scpu_ejtag_loc1,
66*bc8d39a5STzuyi Chang                scpu_ejtag_loc2, acpu_ejtag_loc0, acpu_ejtag_loc1, acpu_ejtag_loc2,
67*bc8d39a5STzuyi Chang                vcpu_ejtag_loc0, vcpu_ejtag_loc1, vcpu_ejtag_loc2, secpu_ejtag_loc0,
68*bc8d39a5STzuyi Chang                secpu_ejtag_loc1, secpu_ejtag_loc2, aucpu_ejtag_loc0, aucpu_ejtag_loc1,
69*bc8d39a5STzuyi Chang                aucpu_ejtag_loc2, iso_tristate, dbg_out0, dbg_out1, standby_dbg,
70*bc8d39a5STzuyi Chang                spdif, arm_trace_debug_disable, arm_trace_debug_enable,
71*bc8d39a5STzuyi Chang                aucpu_ejtag_disable, acpu_ejtag_disable, vcpu_ejtag_disable,
72*bc8d39a5STzuyi Chang                scpu_ejtag_disable, secpu_ejtag_disable, vtc_dmic_loc_disable,
73*bc8d39a5STzuyi Chang                vtc_tdm_disable, vtc_i2si_disable, tdm_ai_disable, ai_disable,
74*bc8d39a5STzuyi Chang                spdif_disable, hif_disable, hif_enable, test_loop, pmic_pwrup ]
75*bc8d39a5STzuyi Chang
76*bc8d39a5STzuyi Chang      drive-strength:
77*bc8d39a5STzuyi Chang        enum: [4, 8]
78*bc8d39a5STzuyi Chang
79*bc8d39a5STzuyi Chang      bias-pull-down: true
80*bc8d39a5STzuyi Chang
81*bc8d39a5STzuyi Chang      bias-pull-up: true
82*bc8d39a5STzuyi Chang
83*bc8d39a5STzuyi Chang      bias-disable: true
84*bc8d39a5STzuyi Chang
85*bc8d39a5STzuyi Chang      input-schmitt-enable: true
86*bc8d39a5STzuyi Chang
87*bc8d39a5STzuyi Chang      input-schmitt-disable: true
88*bc8d39a5STzuyi Chang
89*bc8d39a5STzuyi Chang      drive-push-pull: true
90*bc8d39a5STzuyi Chang
91*bc8d39a5STzuyi Chang      power-source:
92*bc8d39a5STzuyi Chang        description: |
93*bc8d39a5STzuyi Chang          Valid arguments are described as below:
94*bc8d39a5STzuyi Chang          0: power supply of 1.8V
95*bc8d39a5STzuyi Chang          1: power supply of 3.3V
96*bc8d39a5STzuyi Chang        enum: [0, 1]
97*bc8d39a5STzuyi Chang
98*bc8d39a5STzuyi Chang      realtek,drive-strength-p:
99*bc8d39a5STzuyi Chang        description: |
100*bc8d39a5STzuyi Chang          Some of pins can be driven using the P-MOS and N-MOS transistor to
101*bc8d39a5STzuyi Chang          achieve finer adjustments. The block-diagram representation is as
102*bc8d39a5STzuyi Chang          follows:
103*bc8d39a5STzuyi Chang                         VDD
104*bc8d39a5STzuyi Chang                          |
105*bc8d39a5STzuyi Chang                      ||--+
106*bc8d39a5STzuyi Chang               +-----o||     P-MOS-FET
107*bc8d39a5STzuyi Chang               |      ||--+
108*bc8d39a5STzuyi Chang          IN --+          +----- out
109*bc8d39a5STzuyi Chang               |      ||--+
110*bc8d39a5STzuyi Chang               +------||     N-MOS-FET
111*bc8d39a5STzuyi Chang                      ||--+
112*bc8d39a5STzuyi Chang                          |
113*bc8d39a5STzuyi Chang                         GND
114*bc8d39a5STzuyi Chang          The driving strength of the P-MOS/N-MOS transistors impacts the
115*bc8d39a5STzuyi Chang          waveform's rise/fall times. Greater driving strength results in
116*bc8d39a5STzuyi Chang          shorter rise/fall times. Each P-MOS and N-MOS transistor offers
117*bc8d39a5STzuyi Chang          8 configurable levels (0 to 7), with higher values indicating
118*bc8d39a5STzuyi Chang          greater driving strength, contributing to achieving the desired
119*bc8d39a5STzuyi Chang          speed.
120*bc8d39a5STzuyi Chang
121*bc8d39a5STzuyi Chang          The realtek,drive-strength-p is used to control the driving strength
122*bc8d39a5STzuyi Chang          of the P-MOS output.
123*bc8d39a5STzuyi Chang        $ref: /schemas/types.yaml#/definitions/uint32
124*bc8d39a5STzuyi Chang        minimum: 0
125*bc8d39a5STzuyi Chang        maximum: 7
126*bc8d39a5STzuyi Chang
127*bc8d39a5STzuyi Chang      realtek,drive-strength-n:
128*bc8d39a5STzuyi Chang        description: |
129*bc8d39a5STzuyi Chang          Similar to the realtek,drive-strength-p, the realtek,drive-strength-n
130*bc8d39a5STzuyi Chang          is used to control the driving strength of the N-MOS output.
131*bc8d39a5STzuyi Chang        $ref: /schemas/types.yaml#/definitions/uint32
132*bc8d39a5STzuyi Chang        minimum: 0
133*bc8d39a5STzuyi Chang        maximum: 7
134*bc8d39a5STzuyi Chang
135*bc8d39a5STzuyi Chang      realtek,duty-cycle:
136*bc8d39a5STzuyi Chang        description: |
137*bc8d39a5STzuyi Chang          An integer describing the level to adjust output duty cycle, controlling
138*bc8d39a5STzuyi Chang          the proportion of positive and negative waveforms in nanoseconds.
139*bc8d39a5STzuyi Chang          Valid arguments are described as below:
140*bc8d39a5STzuyi Chang          0: 0ns
141*bc8d39a5STzuyi Chang          2: + 0.25ns
142*bc8d39a5STzuyi Chang          3: + 0.5ns
143*bc8d39a5STzuyi Chang          4: -0.25ns
144*bc8d39a5STzuyi Chang          5: -0.5ns
145*bc8d39a5STzuyi Chang        $ref: /schemas/types.yaml#/definitions/uint32
146*bc8d39a5STzuyi Chang        enum: [ 0, 2, 3, 4, 5 ]
147*bc8d39a5STzuyi Chang
148*bc8d39a5STzuyi Chang    required:
149*bc8d39a5STzuyi Chang      - pins
150*bc8d39a5STzuyi Chang
151*bc8d39a5STzuyi Chang    additionalProperties: false
152*bc8d39a5STzuyi Chang
153*bc8d39a5STzuyi Changrequired:
154*bc8d39a5STzuyi Chang  - compatible
155*bc8d39a5STzuyi Chang  - reg
156*bc8d39a5STzuyi Chang
157*bc8d39a5STzuyi ChangadditionalProperties: false
158*bc8d39a5STzuyi Chang
159*bc8d39a5STzuyi Changexamples:
160*bc8d39a5STzuyi Chang  - |
161*bc8d39a5STzuyi Chang     pinctrl@4e000 {
162*bc8d39a5STzuyi Chang         compatible = "realtek,rtd1319d-pinctrl";
163*bc8d39a5STzuyi Chang         reg = <0x4e000 0x130>;
164*bc8d39a5STzuyi Chang
165*bc8d39a5STzuyi Chang         emmc-hs200-pins {
166*bc8d39a5STzuyi Chang             pins = "emmc_clk",
167*bc8d39a5STzuyi Chang                    "emmc_cmd",
168*bc8d39a5STzuyi Chang                    "emmc_data_0",
169*bc8d39a5STzuyi Chang                    "emmc_data_1",
170*bc8d39a5STzuyi Chang                    "emmc_data_2",
171*bc8d39a5STzuyi Chang                    "emmc_data_3",
172*bc8d39a5STzuyi Chang                    "emmc_data_4",
173*bc8d39a5STzuyi Chang                    "emmc_data_5",
174*bc8d39a5STzuyi Chang                    "emmc_data_6",
175*bc8d39a5STzuyi Chang                    "emmc_data_7";
176*bc8d39a5STzuyi Chang             function = "emmc";
177*bc8d39a5STzuyi Chang             realtek,drive-strength-p = <0x2>;
178*bc8d39a5STzuyi Chang             realtek,drive-strength-n = <0x2>;
179*bc8d39a5STzuyi Chang         };
180*bc8d39a5STzuyi Chang
181*bc8d39a5STzuyi Chang         i2c-0-pins {
182*bc8d39a5STzuyi Chang             pins = "gpio_12",
183*bc8d39a5STzuyi Chang                    "gpio_13";
184*bc8d39a5STzuyi Chang             function = "i2c0";
185*bc8d39a5STzuyi Chang             drive-strength = <4>;
186*bc8d39a5STzuyi Chang         };
187*bc8d39a5STzuyi Chang     };
188