xref: /linux/Documentation/devicetree/bindings/pinctrl/qcom,sm8350-tlmm.yaml (revision d6296cb65320be16dbf20f2fd584ddc25f3437cd) 
1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/pinctrl/qcom,sm8350-tlmm.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Qualcomm Technologies, Inc. SM8350 TLMM block
8
9maintainers:
10  - Vinod Koul <vkoul@kernel.org>
11
12description:
13  Top Level Mode Multiplexer pin controller in Qualcomm SM8350 SoC.
14
15allOf:
16  - $ref: /schemas/pinctrl/qcom,tlmm-common.yaml#
17
18properties:
19  compatible:
20    const: qcom,sm8350-tlmm
21
22  reg:
23    maxItems: 1
24
25  interrupts:
26    maxItems: 1
27
28  interrupt-controller: true
29  "#interrupt-cells": true
30  gpio-controller: true
31
32  gpio-reserved-ranges:
33    minItems: 1
34    maxItems: 102
35
36  gpio-line-names:
37    maxItems: 203
38
39  "#gpio-cells": true
40  gpio-ranges: true
41  wakeup-parent: true
42
43required:
44  - compatible
45  - reg
46
47additionalProperties: false
48
49patternProperties:
50  "-state$":
51    oneOf:
52      - $ref: "#/$defs/qcom-sm8350-tlmm-state"
53      - patternProperties:
54          "-pins$":
55            $ref: "#/$defs/qcom-sm8350-tlmm-state"
56        additionalProperties: false
57
58$defs:
59  qcom-sm8350-tlmm-state:
60    type: object
61    description:
62      Pinctrl node's client devices use subnodes for desired pin configuration.
63      Client device subnodes use below standard properties.
64    $ref: qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state
65
66    properties:
67      pins:
68        description:
69          List of gpio pins affected by the properties specified in this
70          subnode.
71        items:
72          oneOf:
73            - pattern: "^gpio([0-9]|[1-9][0-9]|1[0-9][0-9]|20[0-2])$"
74            - enum: [ sdc1_clk, sdc1_cmd, sdc1_data, sdc2_clk, sdc2_cmd, sdc2_data ]
75        minItems: 1
76        maxItems: 36
77
78      function:
79        description:
80          Specify the alternative function to be configured for the specified
81          pins.
82
83        enum: [ atest_char, atest_usb, audio_ref, cam_mclk, cci_async,
84                cci_i2c, cci_timer, cmu_rng, coex_uart1, coex_uart2, cri_trng,
85                cri_trng0, cri_trng1, dbg_out, ddr_bist, ddr_pxi0, ddr_pxi1,
86                ddr_pxi2, ddr_pxi3, dp_hot, dp_lcd, gcc_gp1, gcc_gp2, gcc_gp3,
87                gpio, ibi_i3c, jitter_bist, lpass_slimbus, mdp_vsync, mdp_vsync0,
88                mdp_vsync1, mdp_vsync2, mdp_vsync3, mi2s0_data0, mi2s0_data1,
89                mi2s0_sck, mi2s0_ws, mi2s1_data0, mi2s1_data1, mi2s1_sck,
90                mi2s1_ws, mi2s2_data0, mi2s2_data1, mi2s2_sck, mi2s2_ws,
91                mss_grfc0, mss_grfc1, mss_grfc10, mss_grfc11, mss_grfc12,
92                mss_grfc2, mss_grfc3, mss_grfc4, mss_grfc5, mss_grfc6,
93                mss_grfc7, mss_grfc8, mss_grfc9, nav_gpio, pa_indicator,
94                pcie0_clkreqn, pcie1_clkreqn, phase_flag, pll_bist, pll_clk,
95                pri_mi2s, prng_rosc, qdss_cti, qdss_gpio, qlink0_enable,
96                qlink0_request, qlink0_wmss, qlink1_enable, qlink1_request,
97                qlink1_wmss, qlink2_enable, qlink2_request, qlink2_wmss, qspi0,
98                qspi1, qspi2, qspi3, qspi_clk, qspi_cs, qup0, qup1, qup10,
99                qup11, qup12, qup13, qup14, qup15, qup16, qup17, qup18, qup19,
100                qup2, qup3, qup4, qup5, qup6, qup7, qup8, qup9, qup_l4, qup_l5,
101                qup_l6, sd_write, sdc40, sdc41, sdc42, sdc43, sdc4_clk,
102                sdc4_cmd, sec_mi2s, tb_trig, tgu_ch0, tgu_ch1, tgu_ch2,
103                tgu_ch3, tsense_pwm1, tsense_pwm2, uim0_clk, uim0_data,
104                uim0_present, uim0_reset, uim1_clk, uim1_data, uim1_present,
105                uim1_reset, usb2phy_ac, usb_phy, vfr_0, vfr_1, vsense_trigger ]
106
107
108      bias-disable: true
109      bias-pull-down: true
110      bias-pull-up: true
111      drive-strength: true
112      input-disable: true
113      input-enable: true
114      output-high: true
115      output-low: true
116
117    required:
118      - pins
119
120    additionalProperties: false
121
122examples:
123  - |
124    #include <dt-bindings/interrupt-controller/arm-gic.h>
125    pinctrl@f100000 {
126        compatible = "qcom,sm8350-tlmm";
127        reg = <0x0f100000 0x300000>;
128        interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
129        gpio-controller;
130        #gpio-cells = <2>;
131        interrupt-controller;
132        #interrupt-cells = <2>;
133        gpio-ranges = <&tlmm 0 0 204>; /* GPIOs + ufs_reset */
134
135        gpio-wo-subnode-state {
136            pins = "gpio1";
137            function = "gpio";
138        };
139
140        uart-w-subnodes-state {
141            rx-pins {
142                pins = "gpio18";
143                function = "qup3";
144                bias-pull-up;
145            };
146
147            tx-pins {
148                pins = "gpio19";
149                function = "qup3";
150                bias-disable;
151            };
152        };
153    };
154...
155