1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2%YAML 1.2 3--- 4$id: http://devicetree.org/schemas/pinctrl/qcom,sm8350-tlmm.yaml# 5$schema: http://devicetree.org/meta-schemas/core.yaml# 6 7title: Qualcomm Technologies, Inc. SM8350 TLMM block 8 9maintainers: 10 - Vinod Koul <vkoul@kernel.org> 11 12description: 13 Top Level Mode Multiplexer pin controller in Qualcomm SM8350 SoC. 14 15allOf: 16 - $ref: /schemas/pinctrl/qcom,tlmm-common.yaml# 17 18properties: 19 compatible: 20 const: qcom,sm8350-tlmm 21 22 reg: 23 maxItems: 1 24 25 interrupts: true 26 interrupt-controller: true 27 "#interrupt-cells": true 28 gpio-controller: true 29 gpio-reserved-ranges: true 30 "#gpio-cells": true 31 gpio-ranges: true 32 wakeup-parent: true 33 34required: 35 - compatible 36 - reg 37 38additionalProperties: false 39 40patternProperties: 41 "-state$": 42 oneOf: 43 - $ref: "#/$defs/qcom-sm8350-tlmm-state" 44 - patternProperties: 45 "-pins$": 46 $ref: "#/$defs/qcom-sm8350-tlmm-state" 47 additionalProperties: false 48 49$defs: 50 qcom-sm8350-tlmm-state: 51 type: object 52 description: 53 Pinctrl node's client devices use subnodes for desired pin configuration. 54 Client device subnodes use below standard properties. 55 $ref: qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state 56 57 properties: 58 pins: 59 description: 60 List of gpio pins affected by the properties specified in this 61 subnode. 62 items: 63 oneOf: 64 - pattern: "^gpio([0-9]|[1-9][0-9]|1[0-9][0-9]|20[0-3])$" 65 - enum: [ sdc1_clk, sdc1_cmd, sdc1_data, sdc2_clk, sdc2_cmd, sdc2_data ] 66 minItems: 1 67 maxItems: 36 68 69 function: 70 description: 71 Specify the alternative function to be configured for the specified 72 pins. 73 74 enum: [ atest_char, atest_usb, audio_ref, cam_mclk, cci_async, 75 cci_i2c, cci_timer, cmu_rng, coex_uart1, coex_uart2, cri_trng, 76 cri_trng0, cri_trng1, dbg_out, ddr_bist, ddr_pxi0, ddr_pxi1, 77 ddr_pxi2, ddr_pxi3, dp_hot, dp_lcd, gcc_gp1, gcc_gp2, gcc_gp3, 78 gpio, ibi_i3c, jitter_bist, lpass_slimbus, mdp_vsync, mdp_vsync0, 79 mdp_vsync1, mdp_vsync2, mdp_vsync3, mi2s0_data0, mi2s0_data1, 80 mi2s0_sck, mi2s0_ws, mi2s1_data0, mi2s1_data1, mi2s1_sck, 81 mi2s1_ws, mi2s2_data0, mi2s2_data1, mi2s2_sck, mi2s2_ws, 82 mss_grfc0, mss_grfc1, mss_grfc10, mss_grfc11, mss_grfc12, 83 mss_grfc2, mss_grfc3, mss_grfc4, mss_grfc5, mss_grfc6, 84 mss_grfc7, mss_grfc8, mss_grfc9, nav_gpio, pa_indicator, 85 pcie0_clkreqn, pcie1_clkreqn, phase_flag, pll_bist, pll_clk, 86 pri_mi2s, prng_rosc, qdss_cti, qdss_gpio, qlink0_enable, 87 qlink0_request, qlink0_wmss, qlink1_enable, qlink1_request, 88 qlink1_wmss, qlink2_enable, qlink2_request, qlink2_wmss, qspi0, 89 qspi1, qspi2, qspi3, qspi_clk, qspi_cs, qup0, qup1, qup10, 90 qup11, qup12, qup13, qup14, qup15, qup16, qup17, qup18, qup19, 91 qup2, qup3, qup4, qup5, qup6, qup7, qup8, qup9, qup_l4, qup_l5, 92 qup_l6, sd_write, sdc40, sdc41, sdc42, sdc43, sdc4_clk, 93 sdc4_cmd, sec_mi2s, tb_trig, tgu_ch0, tgu_ch1, tgu_ch2, 94 tgu_ch3, tsense_pwm1, tsense_pwm2, uim0_clk, uim0_data, 95 uim0_present, uim0_reset, uim1_clk, uim1_data, uim1_present, 96 uim1_reset, usb2phy_ac, usb_phy, vfr_0, vfr_1, vsense_trigger ] 97 98 99 bias-disable: true 100 bias-pull-down: true 101 bias-pull-up: true 102 drive-strength: true 103 input-enable: true 104 output-high: true 105 output-low: true 106 107 required: 108 - pins 109 110 additionalProperties: false 111 112examples: 113 - | 114 #include <dt-bindings/interrupt-controller/arm-gic.h> 115 pinctrl@f100000 { 116 compatible = "qcom,sm8350-tlmm"; 117 reg = <0x0f100000 0x300000>; 118 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; 119 gpio-controller; 120 #gpio-cells = <2>; 121 interrupt-controller; 122 #interrupt-cells = <2>; 123 gpio-ranges = <&tlmm 0 0 203>; 124 125 gpio-wo-subnode-state { 126 pins = "gpio1"; 127 function = "gpio"; 128 }; 129 130 uart-w-subnodes-state { 131 rx-pins { 132 pins = "gpio18"; 133 function = "qup3"; 134 bias-pull-up; 135 }; 136 137 tx-pins { 138 pins = "gpio19"; 139 function = "qup3"; 140 bias-disable; 141 }; 142 }; 143 }; 144... 145