1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2%YAML 1.2 3--- 4$id: http://devicetree.org/schemas/pinctrl/qcom,sm6350-tlmm.yaml# 5$schema: http://devicetree.org/meta-schemas/core.yaml# 6 7title: Qualcomm Technologies, Inc. SM6350 TLMM block 8 9maintainers: 10 - Konrad Dybcio <konrad.dybcio@somainline.org> 11 12description: 13 Top Level Mode Multiplexer pin controller in Qualcomm SM6350 SoC. 14 15allOf: 16 - $ref: /schemas/pinctrl/qcom,tlmm-common.yaml# 17 18properties: 19 compatible: 20 const: qcom,sm6350-tlmm 21 22 reg: 23 maxItems: 1 24 25 interrupts: true 26 interrupt-controller: true 27 "#interrupt-cells": true 28 gpio-controller: true 29 gpio-reserved-ranges: true 30 "#gpio-cells": true 31 gpio-ranges: true 32 wakeup-parent: true 33 34required: 35 - compatible 36 - reg 37 38additionalProperties: false 39 40patternProperties: 41 "-state$": 42 oneOf: 43 - $ref: "#/$defs/qcom-sm6350-tlmm-state" 44 - patternProperties: 45 "-pins$": 46 $ref: "#/$defs/qcom-sm6350-tlmm-state" 47 additionalProperties: false 48 49$defs: 50 qcom-sm6350-tlmm-state: 51 type: object 52 description: 53 Pinctrl node's client devices use subnodes for desired pin configuration. 54 Client device subnodes use below standard properties. 55 $ref: qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state 56 57 properties: 58 pins: 59 description: 60 List of gpio pins affected by the properties specified in this 61 subnode. 62 items: 63 oneOf: 64 - pattern: "^gpio([0-9]|[1-9][0-9]|1[0-4][0-9]|15[0-7])$" 65 - enum: [ sdc1_clk, sdc1_cmd, sdc1_data, sdc2_clk, sdc2_cmd, sdc2_data ] 66 minItems: 1 67 maxItems: 36 68 69 function: 70 description: 71 Specify the alternative function to be configured for the specified 72 pins. 73 74 enum: [ adsp_ext, agera_pll, atest_char, atest_char0, atest_char1, atest_char2, 75 atest_char3, atest_tsens, atest_tsens2, atest_usb1, atest_usb10, atest_usb11, 76 atest_usb12, atest_usb13, atest_usb2, atest_usb20, atest_usb21, atest_usb22, 77 atest_usb23, audio_ref, btfm_slimbus, cam_mclk0, cam_mclk1, cam_mclk2, cam_mclk3, 78 cam_mclk4, cci_async, cci_i2c, cci_timer0, cci_timer1, cci_timer2, cci_timer3, 79 cci_timer4, cri_trng, dbg_out, ddr_bist, ddr_pxi0, ddr_pxi1, ddr_pxi2, ddr_pxi3, 80 dp_hot, edp_lcd, gcc_gp1, gcc_gp2, gcc_gp3, gp_pdm0, gp_pdm1, gp_pdm2, gpio, 81 gps_tx, ibi_i3c, jitter_bist, ldo_en, ldo_update, lpass_ext, m_voc, mclk, 82 mdp_vsync, mdp_vsync0, mdp_vsync1, mdp_vsync2, mdp_vsync3, mi2s_0, mi2s_1, mi2s_2, 83 mss_lte, nav_gpio, nav_pps, pa_indicator, pcie0_clk, phase_flag0, phase_flag1, 84 phase_flag10, phase_flag11, phase_flag12, phase_flag13, phase_flag14, phase_flag15, 85 phase_flag16, phase_flag17, phase_flag18, phase_flag19, phase_flag2, phase_flag20, 86 phase_flag21, phase_flag22, phase_flag23, phase_flag24, phase_flag25, phase_flag26, 87 phase_flag27, phase_flag28, phase_flag29, phase_flag3, phase_flag30, phase_flag31, 88 phase_flag4, phase_flag5, phase_flag6, phase_flag7, phase_flag8, phase_flag9, 89 pll_bist, pll_bypassnl, pll_reset, prng_rosc, qdss_cti, qdss_gpio, qdss_gpio0, 90 qdss_gpio1, qdss_gpio10, qdss_gpio11, qdss_gpio12, qdss_gpio13, qdss_gpio14, 91 qdss_gpio15, qdss_gpio2, qdss_gpio3, qdss_gpio4, qdss_gpio5, qdss_gpio6, 92 qdss_gpio7, qdss_gpio8, qdss_gpio9, qlink0_enable, qlink0_request, qlink0_wmss, 93 qlink1_enable, qlink1_request, qlink1_wmss, qup00, qup01, qup02, qup10, qup11, 94 qup12, qup13_f1, qup13_f2, qup14, rffe0_clk, rffe0_data, rffe1_clk, rffe1_data, 95 rffe2_clk, rffe2_data, rffe3_clk, rffe3_data, rffe4_clk, rffe4_data, sd_write, 96 sdc1_tb, sdc2_tb, sp_cmu, tgu_ch0, tgu_ch1, tgu_ch2, tgu_ch3, tsense_pwm1, 97 tsense_pwm2, uim1_clk, uim1_data, uim1_present, uim1_reset, uim2_clk, uim2_data, 98 uim2_present, uim2_reset, usb_phy, vfr_1, vsense_trigger, wlan1_adc0, wlan1_adc1, 99 wlan2_adc0, wlan2_adc1, ] 100 101 102 bias-disable: true 103 bias-pull-down: true 104 bias-pull-up: true 105 drive-strength: true 106 input-enable: true 107 output-high: true 108 output-low: true 109 110 required: 111 - pins 112 113 additionalProperties: false 114 115examples: 116 - | 117 #include <dt-bindings/interrupt-controller/arm-gic.h> 118 pinctrl@f100000 { 119 compatible = "qcom,sm6350-tlmm"; 120 reg = <0x0f100000 0x300000>; 121 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; 122 gpio-controller; 123 #gpio-cells = <2>; 124 interrupt-controller; 125 #interrupt-cells = <2>; 126 gpio-ranges = <&tlmm 0 0 157>; 127 128 gpio-wo-subnode-state { 129 pins = "gpio1"; 130 function = "gpio"; 131 }; 132 133 uart-w-subnodes-state { 134 rx-pins { 135 pins = "gpio25"; 136 function = "qup13_f2"; 137 bias-disable; 138 }; 139 140 tx-pins { 141 pins = "gpio26"; 142 function = "qup13_f2"; 143 bias-disable; 144 }; 145 }; 146 }; 147... 148