xref: /linux/Documentation/devicetree/bindings/pinctrl/qcom,sm6115-tlmm.yaml (revision 24168c5e6dfbdd5b414f048f47f75d64533296ca) 
1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/pinctrl/qcom,sm6115-tlmm.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Qualcomm Technologies, Inc. SM6115, SM4250 TLMM block
8
9maintainers:
10  - Iskren Chernev <iskren.chernev@gmail.com>
11
12description:
13  Top Level Mode Multiplexer pin controller in Qualcomm SM4250 and SM6115
14  SoCs.
15
16properties:
17  compatible:
18    const: qcom,sm6115-tlmm
19
20  reg:
21    maxItems: 3
22
23  reg-names:
24    items:
25      - const: west
26      - const: south
27      - const: east
28
29  interrupts:
30    maxItems: 1
31
32  gpio-reserved-ranges: true
33
34patternProperties:
35  "-state$":
36    oneOf:
37      - $ref: "#/$defs/qcom-sm6115-tlmm-state"
38      - patternProperties:
39          "-pins$":
40            $ref: "#/$defs/qcom-sm6115-tlmm-state"
41        additionalProperties: false
42
43$defs:
44  qcom-sm6115-tlmm-state:
45    type: object
46    description:
47      Pinctrl node's client devices use subnodes for desired pin configuration.
48      Client device subnodes use below standard properties.
49    $ref: qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state
50    unevaluatedProperties: false
51
52    properties:
53      pins:
54        description:
55          List of gpio pins affected by the properties specified in this
56          subnode.
57        items:
58          oneOf:
59            - pattern: "^gpio([0-9]|[1-9][0-9]|10[0-9]|11[0-2])$"
60            - enum: [ sdc1_rclk, sdc1_clk, sdc1_cmd, sdc1_data,
61                      sdc2_clk, sdc2_cmd, sdc2_data, ufs_reset ]
62        minItems: 1
63        maxItems: 36
64
65      function:
66        description:
67          Specify the alternative function to be configured for the specified
68          pins.
69
70        enum: [ adsp_ext, agera_pll, atest, cam_mclk, cci_async, cci_i2c,
71                cci_timer, cri_trng, dac_calib, dbg_out, ddr_bist, ddr_pxi0,
72                ddr_pxi1, ddr_pxi2, ddr_pxi3, gcc_gp1, gcc_gp2, gcc_gp3, gpio,
73                gp_pdm0, gp_pdm1, gp_pdm2, gsm0_tx, gsm1_tx, jitter_bist,
74                mdp_vsync, mdp_vsync_out_0, mdp_vsync_out_1, mpm_pwr, mss_lte,
75                m_voc, nav_gpio, pa_indicator, pbs, pbs_out, phase_flag,
76                pll_bist, pll_bypassnl, pll_reset, prng_rosc, qdss_cti,
77                qdss_gpio, qup0, qup1, qup2, qup3, qup4, qup5, sdc1_tb,
78                sdc2_tb, sd_write, ssbi_wtr1, tgu, tsense_pwm, uim1_clk,
79                uim1_data, uim1_present, uim1_reset, uim2_clk, uim2_data,
80                uim2_present, uim2_reset, usb_phy, vfr_1, vsense_trigger,
81                wlan1_adc0, elan1_adc1 ]
82
83    required:
84      - pins
85
86allOf:
87  - $ref: /schemas/pinctrl/qcom,tlmm-common.yaml#
88
89required:
90  - compatible
91  - reg
92  - reg-names
93
94unevaluatedProperties: false
95
96examples:
97  - |
98    #include <dt-bindings/interrupt-controller/arm-gic.h>
99    tlmm: pinctrl@500000 {
100        compatible = "qcom,sm6115-tlmm";
101        reg = <0x500000 0x400000>,
102              <0x900000 0x400000>,
103              <0xd00000 0x400000>;
104        reg-names = "west", "south", "east";
105        interrupts = <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH>;
106        gpio-controller;
107        #gpio-cells = <2>;
108        interrupt-controller;
109        #interrupt-cells = <2>;
110        gpio-ranges = <&tlmm 0 0 114>;
111
112        sdc2_on_state: sdc2-on-state {
113            clk-pins {
114                pins = "sdc2_clk";
115                bias-disable;
116                drive-strength = <16>;
117            };
118
119            cmd-pins {
120                pins = "sdc2_cmd";
121                bias-pull-up;
122                drive-strength = <10>;
123            };
124
125            data-pins {
126                pins = "sdc2_data";
127                bias-pull-up;
128                drive-strength = <10>;
129            };
130
131            sd-cd-pins {
132                pins = "gpio88";
133                function = "gpio";
134                bias-pull-up;
135                drive-strength = <2>;
136            };
137        };
138    };
139