xref: /linux/Documentation/devicetree/bindings/pinctrl/qcom,sdm845-pinctrl.yaml (revision d6296cb65320be16dbf20f2fd584ddc25f3437cd) 
1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/pinctrl/qcom,sdm845-pinctrl.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Qualcomm SDM845 TLMM pin controller
8
9maintainers:
10  - Bjorn Andersson <andersson@kernel.org>
11  - Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
12
13description:
14  Top Level Mode Multiplexer pin controller in Qualcomm SDM845 SoC.
15
16allOf:
17  - $ref: /schemas/pinctrl/qcom,tlmm-common.yaml#
18
19properties:
20  compatible:
21    const: qcom,sdm845-pinctrl
22
23  reg:
24    maxItems: 1
25
26  interrupts:
27    maxItems: 1
28
29  interrupt-controller: true
30  "#interrupt-cells": true
31  gpio-controller: true
32
33  gpio-reserved-ranges:
34    minItems: 1
35    maxItems: 75
36
37  gpio-line-names:
38    maxItems: 150
39
40  "#gpio-cells": true
41  gpio-ranges: true
42  wakeup-parent: true
43
44patternProperties:
45  "-state$":
46    oneOf:
47      - $ref: "#/$defs/qcom-sdm845-tlmm-state"
48      - patternProperties:
49          "-pins$":
50            $ref: "#/$defs/qcom-sdm845-tlmm-state"
51        additionalProperties: false
52
53  "-hog(-[0-9]+)?$":
54    required:
55      - gpio-hog
56
57$defs:
58  qcom-sdm845-tlmm-state:
59    type: object
60    description:
61      Pinctrl node's client devices use subnodes for desired pin configuration.
62      Client device subnodes use below standard properties.
63    $ref: qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state
64
65    properties:
66      pins:
67        description:
68          List of gpio pins affected by the properties specified in this
69          subnode.
70        items:
71          oneOf:
72            - pattern: "^gpio([0-9]|[1-9][0-9]|1[0-4][0-9])$"
73            - enum: [ ufs_reset, sdc2_clk, sdc2_cmd, sdc2_data ]
74        minItems: 1
75        maxItems: 36
76
77      function:
78        description:
79          Specify the alternative function to be configured for the specified
80          pins.
81        enum: [ adsp_ext, agera_pll, atest_char, atest_tsens, atest_tsens2,
82                atest_usb1, atest_usb10, atest_usb11, atest_usb12, atest_usb13,
83                atest_usb2, atest_usb20, atest_usb21, atest_usb22, atest_usb23,
84                audio_ref, btfm_slimbus, cam_mclk, cci_async, cci_i2c,
85                cci_timer0, cci_timer1, cci_timer2, cci_timer3, cci_timer4,
86                cri_trng, cri_trng0, cri_trng1, dbg_out, ddr_bist, ddr_pxi0,
87                ddr_pxi1, ddr_pxi2, ddr_pxi3, edp_hot, edp_lcd, gcc_gp1,
88                gcc_gp2, gcc_gp3, gpio, jitter_bist, ldo_en, ldo_update,
89                lpass_slimbus, mdp_vsync, mdp_vsync0, mdp_vsync1, mdp_vsync2,
90                mdp_vsync3, mss_lte, m_voc, nav_pps, pa_indicator, pci_e0,
91                pci_e1, phase_flag, pll_bist, pll_bypassnl, pll_reset,
92                pri_mi2s, pri_mi2s_ws, prng_rosc, qdss, qdss_cti, qlink_enable,
93                qlink_request, qspi_clk, qspi_cs, qspi_data, qua_mi2s, qup0,
94                qup1, qup10, qup11, qup12, qup13, qup14, qup15, qup2, qup3,
95                qup4, qup5, qup6, qup7, qup8, qup9, qup_l4, qup_l5, qup_l6,
96                sdc4_clk, sdc4_cmd, sdc4_data, sd_write, sec_mi2s, sp_cmu,
97                spkr_i2s, ter_mi2s, tgu_ch0, tgu_ch1, tgu_ch2, tgu_ch3,
98                tsense_pwm1, tsense_pwm2, tsif1_clk, tsif1_data, tsif1_en,
99                tsif1_error, tsif1_sync, tsif2_clk, tsif2_data, tsif2_en,
100                tsif2_error, tsif2_sync, uim1_clk, uim1_data, uim1_present,
101                uim1_reset, uim2_clk, uim2_data, uim2_present, uim2_reset,
102                uim_batt, usb_phy, vfr_1, vsense_trigger, wlan1_adc0,
103                wlan1_adc1, wlan2_adc0, wlan2_adc1]
104
105      bias-disable: true
106      bias-pull-down: true
107      bias-pull-up: true
108      drive-strength: true
109      input-enable: true
110      output-high: true
111      output-low: true
112
113    required:
114      - pins
115
116    additionalProperties: false
117
118required:
119  - compatible
120  - reg
121
122additionalProperties: false
123
124examples:
125  - |
126    #include <dt-bindings/gpio/gpio.h>
127    #include <dt-bindings/interrupt-controller/arm-gic.h>
128
129    pinctrl@3400000 {
130        compatible = "qcom,sdm845-pinctrl";
131        reg = <0x03400000 0xc00000>;
132        interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
133        gpio-controller;
134        #gpio-cells = <2>;
135        interrupt-controller;
136        #interrupt-cells = <2>;
137        gpio-ranges = <&tlmm 0 0 151>;
138        wakeup-parent = <&pdc_intc>;
139
140        ap-suspend-l-hog {
141            gpio-hog;
142            gpios = <126 GPIO_ACTIVE_LOW>;
143            output-low;
144        };
145
146        cci0-default-state {
147            pins = "gpio17", "gpio18";
148            function = "cci_i2c";
149
150            bias-pull-up;
151            drive-strength = <2>;
152        };
153
154        cam0-default-state {
155            rst-pins {
156                pins = "gpio9";
157                function = "gpio";
158
159                drive-strength = <16>;
160                bias-disable;
161            };
162
163            mclk0-pins {
164                pins = "gpio13";
165                function = "cam_mclk";
166
167                drive-strength = <16>;
168                bias-disable;
169            };
170        };
171    };
172