1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2%YAML 1.2 3--- 4$id: http://devicetree.org/schemas/pinctrl/qcom,sdm670-tlmm.yaml# 5$schema: http://devicetree.org/meta-schemas/core.yaml# 6 7title: Qualcomm Technologies, Inc. SDM670 TLMM block 8 9maintainers: 10 - Richard Acayan <mailingradian@gmail.com> 11 12description: | 13 The Top Level Mode Multiplexer (TLMM) block found in the SDM670 platform. 14 15allOf: 16 - $ref: /schemas/pinctrl/qcom,tlmm-common.yaml# 17 18properties: 19 compatible: 20 const: qcom,sdm670-tlmm 21 22 reg: 23 maxItems: 1 24 25 interrupts: 26 maxItems: 1 27 28 interrupt-controller: true 29 "#interrupt-cells": true 30 gpio-controller: true 31 gpio-reserved-ranges: 32 minItems: 1 33 maxItems: 75 34 35 "#gpio-cells": true 36 gpio-ranges: true 37 wakeup-parent: true 38 39required: 40 - compatible 41 - reg 42 43additionalProperties: false 44 45patternProperties: 46 "-state$": 47 oneOf: 48 - $ref: "#/$defs/qcom-sdm670-tlmm-state" 49 - patternProperties: 50 "-pins$": 51 $ref: "#/$defs/qcom-sdm670-tlmm-state" 52 additionalProperties: false 53 54$defs: 55 qcom-sdm670-tlmm-state: 56 type: object 57 description: 58 Pinctrl node's client devices use subnodes for desired pin configuration. 59 Client device subnodes use below standard properties. 60 $ref: qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state 61 62 properties: 63 pins: 64 description: 65 List of gpio pins affected by the properties specified in this 66 subnode. 67 items: 68 oneOf: 69 - pattern: "^gpio([0-9]|[1-9][0-9]|1[0-4][0-9])$" 70 - enum: [ ufs_reset, sdc1_rclk, sdc1_clk, sdc1_cmd, sdc1_data, 71 sdc2_clk, sdc2_cmd, sdc2_data ] 72 minItems: 1 73 maxItems: 36 74 75 function: 76 description: 77 Specify the alternative function to be configured for the specified 78 pins. 79 80 enum: [ adsp_ext, agera_pll, atest_char, atest_tsens, atest_tsens2, atest_usb1, atest_usb10, 81 atest_usb11, atest_usb12, atest_usb13, atest_usb2, atest_usb20, atest_usb21, 82 atest_usb22, atest_usb23, cam_mclk, cci_async, cci_i2c, cci_timer0, cci_timer1, 83 cci_timer2, cci_timer3, cci_timer4, copy_gp, copy_phase, dbg_out, ddr_bist, 84 ddr_pxi0, ddr_pxi1, ddr_pxi2, ddr_pxi3, edp_hot, edp_lcd, gcc_gp1, gcc_gp2, gcc_gp3, 85 gp_pdm0, gp_pdm1, gp_pdm2, gpio, gps_tx, jitter_bist, ldo_en, ldo_update, 86 lpass_slimbus, m_voc, mdp_vsync, mdp_vsync0, mdp_vsync1, mdp_vsync2, mdp_vsync3, 87 mss_lte, nav_pps, pa_indicator, pci_e0, pci_e1, phase_flag, pll_bist, pll_bypassnl, 88 pll_reset, pri_mi2s, pri_mi2s_ws, prng_rosc, qdss_cti, qdss, qlink_enable, 89 qlink_request, qua_mi2s, qup0, qup1, qup10, qup11, qup12, qup13, qup14, qup15, qup2, 90 qup3, qup4, qup5, qup6, qup7, qup8, qup9, qup_l4, qup_l5, qup_l6, sdc4_clk, 91 sdc4_cmd, sdc4_data, sd_write, sec_mi2s, ter_mi2s, tgu_ch0, tgu_ch1, tgu_ch2, 92 tgu_ch3, tsif1_clk, tsif1_data, tsif1_en, tsif1_error, tsif1_sync, tsif2_clk, 93 tsif2_data, tsif2_en, tsif2_error, tsif2_sync, uim1_clk, uim1_data, uim1_present, 94 uim1_reset, uim2_clk, uim2_data, uim2_present, uim2_reset, uim_batt, usb_phy, vfr_1, 95 vsense_trigger, wlan1_adc0, wlan1_adc1, wlan2_adc0, wlan2_adc1, wsa_clk, wsa_data, ] 96 97 98 bias-disable: true 99 bias-pull-down: true 100 bias-pull-up: true 101 drive-strength: true 102 input-enable: true 103 output-high: true 104 output-low: true 105 106 required: 107 - pins 108 109 additionalProperties: false 110 111examples: 112 - | 113 #include <dt-bindings/interrupt-controller/arm-gic.h> 114 pinctrl@3400000 { 115 compatible = "qcom,sdm670-tlmm"; 116 reg = <0x03400000 0x300000>; 117 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; 118 gpio-controller; 119 #gpio-cells = <2>; 120 interrupt-controller; 121 #interrupt-cells = <2>; 122 gpio-ranges = <&tlmm 0 0 151>; 123 124 qup-i2c9-state { 125 pins = "gpio6", "gpio7"; 126 function = "qup9"; 127 }; 128 }; 129... 130