xref: /linux/Documentation/devicetree/bindings/pinctrl/qcom,sc7280-lpass-lpi-pinctrl.yaml (revision da1d9caf95def6f0320819cf941c9fd1069ba9e1) 
1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/pinctrl/qcom,sc7280-lpass-lpi-pinctrl.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Qualcomm Technologies, Inc. Low Power Audio SubSystem (LPASS)
8  Low Power Island (LPI) TLMM block
9
10maintainers:
11  - Srinivasa Rao Mandadapu <srivasam@codeaurora.org>
12  - Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
13
14description: |
15  This binding describes the Top Level Mode Multiplexer block found in the
16  LPASS LPI IP on most Qualcomm SoCs
17
18properties:
19  compatible:
20    const: qcom,sc7280-lpass-lpi-pinctrl
21
22  reg:
23    minItems: 2
24    maxItems: 2
25
26  gpio-controller: true
27
28  '#gpio-cells':
29    description: Specifying the pin number and flags, as defined in
30      include/dt-bindings/gpio/gpio.h
31    const: 2
32
33  gpio-ranges:
34    maxItems: 1
35
36#PIN CONFIGURATION NODES
37patternProperties:
38  '-pins$':
39    type: object
40    description:
41      Pinctrl node's client devices use subnodes for desired pin configuration.
42      Client device subnodes use below standard properties.
43    $ref: "/schemas/pinctrl/pincfg-node.yaml"
44
45    properties:
46      pins:
47        description:
48          List of gpio pins affected by the properties specified in this
49          subnode.
50        items:
51          oneOf:
52            - pattern: "^gpio([0-9]|[1-9][0-9])$"
53        minItems: 1
54        maxItems: 15
55
56      function:
57        enum: [ gpio, swr_tx_clk, qua_mi2s_sclk, swr_tx_data, qua_mi2s_ws,
58                qua_mi2s_data, swr_rx_clk, swr_rx_data, dmic1_clk, i2s1_clk,
59                dmic1_data, i2s1_ws, dmic2_clk, dmic2_data, i2s1_data,
60                i2s2_clk, wsa_swr_clk, i2s2_ws, wsa_swr_data, dmic3_clk,
61                dmic3_data, i2s2_data ]
62        description:
63          Specify the alternative function to be configured for the specified
64          pins.
65
66      drive-strength:
67        enum: [2, 4, 6, 8, 10, 12, 14, 16]
68        default: 2
69        description:
70          Selects the drive strength for the specified pins, in mA.
71
72      slew-rate:
73        enum: [0, 1, 2, 3]
74        default: 0
75        description: |
76            0: No adjustments
77            1: Higher Slew rate (faster edges)
78            2: Lower Slew rate (slower edges)
79            3: Reserved (No adjustments)
80
81      bias-pull-down: true
82
83      bias-pull-up: true
84
85      bias-disable: true
86
87      output-high: true
88
89      output-low: true
90
91    required:
92      - pins
93      - function
94
95    additionalProperties: false
96
97required:
98  - compatible
99  - reg
100  - gpio-controller
101  - '#gpio-cells'
102  - gpio-ranges
103
104additionalProperties: false
105
106examples:
107  - |
108    lpass_tlmm: pinctrl@33c0000 {
109        compatible = "qcom,sc7280-lpass-lpi-pinctrl";
110        reg = <0x33c0000 0x20000>,
111              <0x3550000 0x10000>;
112        gpio-controller;
113        #gpio-cells = <2>;
114        gpio-ranges = <&lpass_tlmm 0 0 15>;
115    };
116