xref: /linux/Documentation/devicetree/bindings/pinctrl/qcom,sar2130p-tlmm.yaml (revision 9ad8d22f2f3fad7a366c9772362795ef6d6a2d51) 
1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/pinctrl/qcom,sar2130p-tlmm.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Qualcomm Technologies, Inc. SAR2130P TLMM block
8
9maintainers:
10  - Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
11
12description:
13  Top Level Mode Multiplexer pin controller in Qualcomm SAR2130P SoC.
14
15allOf:
16  - $ref: /schemas/pinctrl/qcom,tlmm-common.yaml#
17
18properties:
19  compatible:
20    const: qcom,sar2130p-tlmm
21
22  reg:
23    maxItems: 1
24
25  interrupts:
26    maxItems: 1
27
28  gpio-reserved-ranges:
29    minItems: 1
30    maxItems: 78
31
32  gpio-line-names:
33    maxItems: 156
34
35patternProperties:
36  "-state$":
37    oneOf:
38      - $ref: "#/$defs/qcom-sar2130p-tlmm-state"
39      - patternProperties:
40          "-pins$":
41            $ref: "#/$defs/qcom-sar2130p-tlmm-state"
42        additionalProperties: false
43
44$defs:
45  qcom-sar2130p-tlmm-state:
46    type: object
47    description:
48      Pinctrl node's client devices use subnodes for desired pin configuration.
49      Client device subnodes use below standard properties.
50    $ref: qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state
51    unevaluatedProperties: false
52
53    properties:
54      pins:
55        description:
56          List of gpio pins affected by the properties specified in this
57          subnode.
58        items:
59          oneOf:
60            - pattern: "^gpio([0-9]|[1-9][0-9]|1[0-4][0-9]|15[0-5])$"
61            - enum: [ sdc1_clk, sdc1_cmd, sdc1_data, sdc1_rclk ]
62        minItems: 1
63        maxItems: 36
64
65      function:
66        description:
67          Specify the alternative function to be configured for the specified
68          pins.
69        enum: [ aoss_cti, atest_char, atest_char0, atest_char1, atest_char2,
70                atest_char3, atest_usb0, atest_usb00, atest_usb01, atest_usb02,
71                atest_usb03, audio_ref, cam_mclk, cci_async, cci_i2c,
72                cci_timer0, cci_timer1, cci_timer2, cci_timer3, cci_timer4,
73                cri_trng, cri_trng0, cri_trng1, dbg_out, ddr_bist, ddr_pxi0,
74                ddr_pxi1, ddr_pxi2, ddr_pxi3, dp0_hot, ext_mclk0, ext_mclk1,
75                gcc_gp1, gcc_gp2, gcc_gp3, gpio, host2wlan_sol, i2s0_data0,
76                i2s0_data1, i2s0_sck, i2s0_ws, ibi_i3c, jitter_bist, mdp_vsync,
77                mdp_vsync0, mdp_vsync1, mdp_vsync2, mdp_vsync3, pcie0_clkreqn,
78                pcie1_clkreqn, phase_flag0, phase_flag1, phase_flag10,
79                phase_flag11, phase_flag12, phase_flag13, phase_flag14,
80                phase_flag15, phase_flag16, phase_flag17, phase_flag18,
81                phase_flag19, phase_flag2, phase_flag20, phase_flag21,
82                phase_flag22, phase_flag23, phase_flag24, phase_flag25,
83                phase_flag26, phase_flag27, phase_flag28, phase_flag29,
84                phase_flag3, phase_flag30, phase_flag31, phase_flag4,
85                phase_flag5, phase_flag6, phase_flag7, phase_flag8,
86                phase_flag9, pll_bist, pll_clk, prng_rosc0, prng_rosc1,
87                prng_rosc2, prng_rosc3, qdss_cti, qdss_gpio, qdss_gpio0,
88                qdss_gpio1, qdss_gpio10, qdss_gpio11, qdss_gpio12, qdss_gpio13,
89                qdss_gpio14, qdss_gpio15, qdss_gpio2, qdss_gpio3, qdss_gpio4,
90                qdss_gpio5, qdss_gpio6, qdss_gpio7, qdss_gpio8, qdss_gpio9,
91                qspi0, qspi1, qspi2, qspi3, qspi_clk, qspi_cs0, qspi_cs1, qup0,
92                qup1, qup2, qup3, qup4, qup5, qup6, qup7, qup8, qup9, qup10,
93                qup11, tb_trig, tgu_ch0, tgu_ch1, tgu_ch2, tgu_ch3,
94                tmess_prng0, tmess_prng1, tmess_prng2, tmess_prng3,
95                tsense_pwm1, tsense_pwm2, usb0_phy, vsense_trigger ]
96
97    required:
98      - pins
99
100required:
101  - compatible
102  - reg
103
104unevaluatedProperties: false
105
106examples:
107  - |
108    #include <dt-bindings/interrupt-controller/arm-gic.h>
109    pinctrl@f100000 {
110        compatible = "qcom,sar2130p-tlmm";
111        reg = <0x0f100000 0x300000>;
112        gpio-controller;
113        #gpio-cells = <2>;
114        gpio-ranges = <&tlmm 0 0 156>;
115        interrupt-controller;
116        #interrupt-cells = <2>;
117        interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
118
119        gpio-wo-state {
120            pins = "gpio1";
121            function = "gpio";
122        };
123
124        uart-w-state {
125            rx-pins {
126                pins = "gpio26";
127                function = "qup7";
128                bias-pull-up;
129            };
130
131            tx-pins {
132                pins = "gpio27";
133                function = "qup7";
134                bias-disable;
135            };
136        };
137    };
138...
139