xref: /linux/Documentation/devicetree/bindings/pinctrl/qcom,sa8775p-tlmm.yaml (revision 9ad8d22f2f3fad7a366c9772362795ef6d6a2d51) 
1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/pinctrl/qcom,sa8775p-tlmm.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Qualcomm Technologies, Inc. SA8775P TLMM block
8
9maintainers:
10  - Bartosz Golaszewski <bartosz.golaszewski@linaro.org>
11
12description: |
13  Top Level Mode Multiplexer pin controller in Qualcomm SA8775P SoC.
14
15allOf:
16  - $ref: /schemas/pinctrl/qcom,tlmm-common.yaml#
17
18properties:
19  compatible:
20    oneOf:
21      - items:
22          - enum:
23              - qcom,sa8255p-tlmm
24          - const: qcom,sa8775p-tlmm
25      - items:
26          - const: qcom,sa8775p-tlmm
27
28  reg:
29    maxItems: 1
30
31  interrupts:
32    maxItems: 1
33
34  gpio-reserved-ranges:
35    minItems: 1
36    maxItems: 74
37
38  gpio-line-names:
39    maxItems: 148
40
41patternProperties:
42  "-state$":
43    oneOf:
44      - $ref: "#/$defs/qcom-sa8775p-tlmm-state"
45      - patternProperties:
46          "-pins$":
47            $ref: "#/$defs/qcom-sa8775p-tlmm-state"
48        additionalProperties: false
49
50$defs:
51  qcom-sa8775p-tlmm-state:
52    type: object
53    description:
54      Pinctrl node's client devices use subnodes for desired pin configuration.
55      Client device subnodes use below standard properties.
56    $ref: qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state
57    unevaluatedProperties: false
58
59    properties:
60      pins:
61        description:
62          List of gpio pins affected by the properties specified in this
63          subnode.
64        items:
65          oneOf:
66            - pattern: "^gpio([0-9]|[1-9][0-9]|1[0-3][0-9]|14[0-7])$"
67            - enum: [ sdc1_clk, sdc1_cmd, sdc1_data, sdc1_rclk, ufs_reset ]
68        minItems: 1
69        maxItems: 16
70
71      function:
72        description:
73          Specify the alternative function to be configured for the specified
74          pins.
75
76        enum: [ atest_char, atest_usb2, audio_ref, cam_mclk, cci_async, cci_i2c,
77                cci_timer0, cci_timer1, cci_timer2, cci_timer3, cci_timer4,
78                cci_timer5, cci_timer6, cci_timer7, cci_timer8, cci_timer9,
79                cri_trng, cri_trng0, cri_trng1, dbg_out, ddr_bist, ddr_pxi0,
80                ddr_pxi1, ddr_pxi2, ddr_pxi3, ddr_pxi4, ddr_pxi5, edp0_hot,
81                edp0_lcd, edp1_hot, edp1_lcd, edp2_hot, edp2_lcd, edp3_hot,
82                edp3_lcd, emac0_mcg0, emac0_mcg1, emac0_mcg2, emac0_mcg3,
83                emac0_mdc, emac0_mdio, emac0_ptp_aux, emac0_ptp_pps, emac1_mcg0,
84                emac1_mcg1, emac1_mcg2, emac1_mcg3, emac1_mdc, emac1_mdio,
85                emac1_ptp_aux, emac1_ptp_pps, gcc_gp1, gcc_gp2, gcc_gp3,
86                gcc_gp4, gcc_gp5, gpio, hs0_mi2s, hs1_mi2s, hs2_mi2s, ibi_i3c,
87                jitter_bist, mdp0_vsync0, mdp0_vsync1, mdp0_vsync2, mdp0_vsync3,
88                mdp0_vsync4, mdp0_vsync5, mdp0_vsync6, mdp0_vsync7, mdp0_vsync8,
89                mdp1_vsync0, mdp1_vsync1, mdp1_vsync2, mdp1_vsync3, mdp1_vsync4,
90                mdp1_vsync5, mdp1_vsync6, mdp1_vsync7, mdp1_vsync8, mdp_vsync,
91                mi2s1_data0, mi2s1_data1, mi2s1_sck, mi2s1_ws, mi2s2_data0,
92                mi2s2_data1, mi2s2_sck, mi2s2_ws, mi2s_mclk0, mi2s_mclk1,
93                pcie0_clkreq, pcie1_clkreq, phase_flag, pll_bist, pll_clk,
94                prng_rosc0, prng_rosc1, prng_rosc2, prng_rosc3, qdss_cti,
95                qdss_gpio, qup0_se0, qup0_se1, qup0_se2, qup0_se3, qup0_se4,
96                qup0_se5, qup1_se0, qup1_se1, qup1_se2, qup1_se3, qup1_se4,
97                qup1_se5, qup1_se6, qup2_se0, qup2_se1, qup2_se2, qup2_se3,
98                qup2_se4, qup2_se5, qup2_se6, qup3_se0, sailss_emac0,
99                sailss_ospi, sail_top, sgmii_phy, tb_trig, tgu_ch0, tgu_ch1,
100                tgu_ch2, tgu_ch3, tgu_ch4, tgu_ch5, tsense_pwm1, tsense_pwm2,
101                tsense_pwm3, tsense_pwm4, usb2phy_ac, vsense_trigger ]
102
103    required:
104      - pins
105
106required:
107  - compatible
108  - reg
109
110unevaluatedProperties: false
111
112examples:
113  - |
114    #include <dt-bindings/interrupt-controller/arm-gic.h>
115
116    tlmm: pinctrl@f000000 {
117        compatible = "qcom,sa8775p-tlmm";
118        reg = <0xf000000 0x1000000>;
119        interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
120        gpio-controller;
121        #gpio-cells = <2>;
122        interrupt-controller;
123        #interrupt-cells = <2>;
124        gpio-ranges = <&tlmm 0 0 148>;
125
126        qup-uart10-state {
127            pins = "gpio46", "gpio47";
128            function = "qup1_se3";
129        };
130    };
131...
132