1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2%YAML 1.2 3--- 4$id: http://devicetree.org/schemas/pinctrl/qcom,qdu1000-tlmm.yaml# 5$schema: http://devicetree.org/meta-schemas/core.yaml# 6 7title: Qualcomm Technologies, Inc. QDU1000/QRU1000 TLMM block 8 9maintainers: 10 - Melody Olvera <quic_molvera@quicinc.com> 11 12description: | 13 Top Level Mode Multiplexer pin controller found in the QDU1000 and 14 QRU1000 SoCs. 15 16allOf: 17 - $ref: /schemas/pinctrl/qcom,tlmm-common.yaml# 18 19properties: 20 compatible: 21 const: qcom,qdu1000-tlmm 22 23 reg: 24 maxItems: 1 25 26 interrupts: true 27 interrupt-controller: true 28 "#interrupt-cells": true 29 gpio-controller: true 30 31 gpio-reserved-ranges: 32 minItems: 1 33 maxItems: 76 34 35 gpio-line-names: 36 maxItems: 151 37 38 "#gpio-cells": true 39 gpio-ranges: true 40 wakeup-parent: true 41 42patternProperties: 43 "-state$": 44 oneOf: 45 - $ref: "#/$defs/qcom-qdu1000-tlmm-state" 46 - patternProperties: 47 "-pins$": 48 $ref: "#/$defs/qcom-qdu1000-tlmm-state" 49 additionalProperties: false 50 51$defs: 52 qcom-qdu1000-tlmm-state: 53 type: object 54 description: 55 Pinctrl node's client devices use subnodes for desired pin configuration. 56 Client device subnodes use below standard properties. 57 $ref: qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state 58 59 properties: 60 pins: 61 description: 62 List of gpio pins affected by the properties specified in this 63 subnode. 64 items: 65 oneOf: 66 - pattern: "^gpio([0-9]|[1-9][0-9]|1[0-4][0-9]|150)$" 67 - enum: [ sdc1_rclk, sdc1_clk, sdc1_cmd, sdc1_data ] 68 minItems: 1 69 maxItems: 36 70 71 function: 72 description: 73 Specify the alternative function to be configured for the specified 74 pins. 75 enum: [ atest_char, atest_usb, char_exec, CMO_PRI, cmu_rng, 76 dbg_out_clk, ddr_bist, ddr_pxi1, ddr_pxi2, ddr_pxi3, ddr_pxi4, 77 ddr_pxi5, ddr_pxi6, ddr_pxi7, eth012_int_n, eth345_int_n, 78 gcc_gp1, gcc_gp2, gcc_gp3, gpio, gps_pps_in, hardsync_pps_in, 79 intr_c, jitter_bist_ref, pcie_clkreqn, phase_flag, pll_bist, 80 pll_clk, prng_rosc, qdss_cti, qdss_gpio, qlink0_enable, 81 qlink0_request, qlink0_wmss, qlink1_enable, qlink1_request, 82 qlink1_wmss, qlink2_enable, qlink2_request, qlink2_wmss, 83 qlink3_enable, qlink3_request, qlink3_wmss, qlink4_enable, 84 qlink4_request, qlink4_wmss, qlink5_enable, qlink5_request, 85 qlink5_wmss, qlink6_enable, qlink6_request, qlink6_wmss, 86 qlink7_enable, qlink7_request, qlink7_wmss, qspi_clk, qspi_cs, 87 qspi0, qspi1, qspi2, qspi3, qup00, qup01, qup02, qup03, qup04, 88 qup05, qup06, qup07, qup08, qup10, qup11, qup12, qup13, qup14, 89 qup15, qup16, qup17, qup20, qup21, qup22, SI5518_INT, smb_alert, 90 smb_clk, smb_dat, tb_trig, tgu_ch0, tgu_ch1, tgu_ch2, tgu_ch3, 91 tgu_ch4, tgu_ch5, tgu_ch6, tgu_ch7, tmess_prng0, tmess_prng1, 92 tmess_prng2, tmess_prng3, tod_pps_in, tsense_pwm1, tsense_pwm2, 93 usb2phy_ac, usb_con_det, usb_dfp_en, usb_phy, vfr_0, vfr_1, 94 vsense_trigger ] 95 96 bias-disable: true 97 bias-pull-down: true 98 bias-pull-up: true 99 drive-strength: true 100 input-enable: true 101 output-high: true 102 output-low: true 103 104 required: 105 - pins 106 107 additionalProperties: false 108 109required: 110 - compatible 111 - reg 112 113additionalProperties: false 114 115examples: 116 - | 117 #include <dt-bindings/interrupt-controller/arm-gic.h> 118 119 pinctrl@f000000 { 120 compatible = "qcom,qdu1000-tlmm"; 121 reg = <0xf000000 0x1000000>; 122 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; 123 gpio-controller; 124 #gpio-cells = <2>; 125 interrupt-controller; 126 #interrupt-cells = <2>; 127 gpio-ranges = <&tlmm 0 0 151>; 128 wakeup-parent = <&pdc>; 129 130 uart0-default-state { 131 pins = "gpio6", "gpio7", "gpio8", "gpio9"; 132 function = "qup00"; 133 }; 134 }; 135