xref: /linux/Documentation/devicetree/bindings/pinctrl/qcom,qcs615-tlmm.yaml (revision 9ad8d22f2f3fad7a366c9772362795ef6d6a2d51) 
1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/pinctrl/qcom,qcs615-tlmm.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Qualcomm Technologies, Inc. QCS615 TLMM block
8
9maintainers:
10  - Lijuan Gao <quic_lijuang@quicinc.com>
11
12description:
13  Top Level Mode Multiplexer pin controller in Qualcomm QCS615 SoC.
14
15allOf:
16  - $ref: /schemas/pinctrl/qcom,tlmm-common.yaml#
17
18properties:
19  compatible:
20    const: qcom,qcs615-tlmm
21
22  reg:
23    maxItems: 3
24
25  reg-names:
26    items:
27      - const: east
28      - const: west
29      - const: south
30
31  interrupts:
32    maxItems: 1
33
34  gpio-reserved-ranges:
35    minItems: 1
36    maxItems: 62
37
38  gpio-line-names:
39    maxItems: 123
40
41patternProperties:
42  "-state$":
43    oneOf:
44      - $ref: "#/$defs/qcom-qcs615-tlmm-state"
45      - type: object
46        patternProperties:
47          "-pins$":
48            $ref: "#/$defs/qcom-qcs615-tlmm-state"
49        additionalProperties: false
50
51$defs:
52  qcom-qcs615-tlmm-state:
53    type: object
54    description:
55      Pinctrl node's client devices use subnodes for desired pin configuration.
56      Client device subnodes use below standard properties.
57    $ref: qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state
58    unevaluatedProperties: false
59
60    properties:
61      pins:
62        description:
63          List of gpio pins affected by the properties specified in this
64          subnode.
65        items:
66          oneOf:
67            - pattern: "^gpio([0-9]|[1-9][0-9]|1[0-1][0-9]|12[0-2])$"
68            - enum: [ sdc1_clk, sdc1_cmd, sdc1_data, sdc1_rclk,
69                      sdc2_clk, sdc2_cmd, sdc2_data, ufs_reset ]
70        minItems: 1
71        maxItems: 36
72
73      function:
74        description:
75          Specify the alternative function to be configured for the specified
76          pins.
77        enum: [ gpio, adsp_ext, agera_pll, aoss_cti, atest_char, atest_tsens,
78                atest_usb, cam_mclk, cci_async, cci_i2c, cci_timer, copy_gp,
79                copy_phase, cri_trng, dbg_out_clk, ddr_bist, ddr_pxi, dp_hot,
80                edp_hot, edp_lcd, emac_gcc, emac_phy_intr, forced_usb, gcc_gp,
81                gp_pdm, gps_tx, hs0_mi2s, hs1_mi2s, jitter_bist, ldo_en,
82                ldo_update, m_voc, mclk1, mclk2, mdp_vsync, mdp_vsync0_out,
83                mdp_vsync1_out, mdp_vsync2_out, mdp_vsync3_out, mdp_vsync4_out,
84                mdp_vsync5_out, mi2s_1, mss_lte, nav_pps_in, nav_pps_out,
85                pa_indicator_or, pcie_clk_req, pcie_ep_rst, phase_flag, pll_bist,
86                pll_bypassnl, pll_reset_n, prng_rosc, qdss_cti, qdss_gpio,
87                qlink_enable, qlink_request, qspi, qup0, qup1, rgmii,
88                sd_write_protect, sp_cmu, ter_mi2s, tgu_ch, uim1, uim2, usb0_hs,
89                usb1_hs, usb_phy_ps, vfr_1, vsense_trigger_mirnat, wlan, wsa_clk,
90                wsa_data ]
91
92    required:
93      - pins
94
95required:
96  - compatible
97  - reg
98  - reg-names
99
100unevaluatedProperties: false
101
102examples:
103  - |
104    #include <dt-bindings/interrupt-controller/arm-gic.h>
105
106    tlmm: pinctrl@3000000 {
107        compatible = "qcom,qcs615-tlmm";
108        reg = <0x03100000 0x300000>,
109              <0x03500000 0x300000>,
110              <0x03c00000 0x300000>;
111        reg-names = "east", "west", "south";
112        interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
113        gpio-ranges = <&tlmm 0 0 123>;
114        gpio-controller;
115        #gpio-cells = <2>;
116        interrupt-controller;
117        #interrupt-cells = <2>;
118
119        qup3-uart2-state {
120            pins ="gpio16", "gpio17";
121            function = "qup0";
122        };
123    };
124...
125