xref: /linux/Documentation/devicetree/bindings/pinctrl/qcom,msm8226-pinctrl.yaml (revision d6296cb65320be16dbf20f2fd584ddc25f3437cd) 
1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/pinctrl/qcom,msm8226-pinctrl.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Qualcomm Technologies, Inc. MSM8226 TLMM block
8
9maintainers:
10  - Bjorn Andersson <bjorn.andersson@linaro.org>
11
12description:
13  Top Level Mode Multiplexer pin controller in Qualcomm MSM8226 SoC.
14
15properties:
16  compatible:
17    const: qcom,msm8226-pinctrl
18
19  reg:
20    description: Specifies the base address and size of the TLMM register space
21    maxItems: 1
22
23  interrupts:
24    maxItems: 1
25
26  interrupt-controller: true
27  "#interrupt-cells": true
28  gpio-controller: true
29  "#gpio-cells": true
30  gpio-ranges: true
31
32  gpio-reserved-ranges:
33    maxItems: 1
34
35patternProperties:
36  "-state$":
37    oneOf:
38      - $ref: "#/$defs/qcom-msm8226-tlmm-state"
39      - patternProperties:
40          "-pins$":
41            $ref: "#/$defs/qcom-msm8226-tlmm-state"
42        additionalProperties: false
43
44$defs:
45  qcom-msm8226-tlmm-state:
46    type: object
47    description:
48      Pinctrl node's client devices use subnodes for desired pin configuration.
49      Client device subnodes use below standard properties.
50    $ref: qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state
51
52    properties:
53      pins:
54        description:
55          List of gpio pins affected by the properties specified in this
56          subnode.
57        items:
58          oneOf:
59            - pattern: "^gpio([0-9]|[1-9][0-9]|10[0-9]|11[0-6])$"
60            - enum: [ sdc1_clk, sdc1_cmd, sdc1_data, sdc2_clk, sdc2_cmd, sdc2_data ]
61        minItems: 1
62        maxItems: 36
63
64      function:
65        description:
66          Specify the alternative function to be configured for the specified
67          pins. Functions are only valid for gpio pins.
68        enum: [ gpio, cci_i2c0, blsp_uim1, blsp_uim2, blsp_uim3, blsp_uim5,
69                blsp_i2c1, blsp_i2c2, blsp_i2c3, blsp_i2c4, blsp_i2c5, blsp_spi1,
70                blsp_spi2, blsp_spi3, blsp_spi5, blsp_uart1, blsp_uart2,
71                blsp_uart3, blsp_uart4, blsp_uart5, cam_mclk0, cam_mclk1,
72                gp0_clk, gp1_clk, sdc3, wlan ]
73
74      bias-pull-down: true
75      bias-pull-up: true
76      bias-disable: true
77      drive-strength: true
78      input-enable: true
79      output-high: true
80      output-low: true
81
82    required:
83      - pins
84
85    additionalProperties: false
86
87allOf:
88  - $ref: /schemas/pinctrl/qcom,tlmm-common.yaml#
89
90required:
91  - compatible
92  - reg
93
94additionalProperties: false
95
96examples:
97  - |
98    #include <dt-bindings/interrupt-controller/arm-gic.h>
99    msmgpio: pinctrl@fd510000 {
100        compatible = "qcom,msm8226-pinctrl";
101        reg = <0xfd510000 0x4000>;
102
103        gpio-controller;
104        #gpio-cells = <2>;
105        gpio-ranges = <&msmgpio 0 0 117>;
106        interrupt-controller;
107        #interrupt-cells = <2>;
108        interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
109
110        serial-state {
111            pins = "gpio8", "gpio9";
112            function = "blsp_uart3";
113            drive-strength = <8>;
114            bias-disable;
115        };
116    };
117