xref: /linux/Documentation/devicetree/bindings/pinctrl/qcom,msm8226-pinctrl.yaml (revision 07f0148aafe8c95a3a76cd59e9e75b4d78d1d31d) 
1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/pinctrl/qcom,msm8226-pinctrl.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Qualcomm Technologies, Inc. MSM8226 TLMM block
8
9maintainers:
10  - Bjorn Andersson <bjorn.andersson@linaro.org>
11
12description:
13  Top Level Mode Multiplexer pin controller in Qualcomm MSM8226 SoC.
14
15properties:
16  compatible:
17    const: qcom,msm8226-pinctrl
18
19  reg:
20    description: Specifies the base address and size of the TLMM register space
21    maxItems: 1
22
23  interrupts: true
24  interrupt-controller: true
25  "#interrupt-cells": true
26  gpio-controller: true
27  "#gpio-cells": true
28  gpio-ranges: true
29
30  gpio-reserved-ranges:
31    maxItems: 1
32
33patternProperties:
34  "-state$":
35    oneOf:
36      - $ref: "#/$defs/qcom-msm8226-tlmm-state"
37      - patternProperties:
38          "-pins$":
39            $ref: "#/$defs/qcom-msm8226-tlmm-state"
40        additionalProperties: false
41
42$defs:
43  qcom-msm8226-tlmm-state:
44    type: object
45    description:
46      Pinctrl node's client devices use subnodes for desired pin configuration.
47      Client device subnodes use below standard properties.
48    $ref: qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state
49
50    properties:
51      pins:
52        description:
53          List of gpio pins affected by the properties specified in this
54          subnode.
55        items:
56          oneOf:
57            - pattern: "^gpio([0-9]|[1-9][0-9]|1[0-1][0-6])$"
58            - enum: [ sdc1_clk, sdc1_cmd, sdc1_data, sdc2_clk, sdc2_cmd, sdc2_data ]
59        minItems: 1
60        maxItems: 36
61
62      function:
63        description:
64          Specify the alternative function to be configured for the specified
65          pins. Functions are only valid for gpio pins.
66        enum: [ gpio, cci_i2c0, blsp_uim1, blsp_uim2, blsp_uim3, blsp_uim5,
67                blsp_i2c1, blsp_i2c2, blsp_i2c3, blsp_i2c4, blsp_i2c5, blsp_spi1,
68                blsp_spi2, blsp_spi3, blsp_spi5, blsp_uart1, blsp_uart2,
69                blsp_uart3, blsp_uart4, blsp_uart5, cam_mclk0, cam_mclk1, sdc3,
70                wlan ]
71
72      bias-pull-down: true
73      bias-pull-up: true
74      bias-disable: true
75      drive-strength: true
76      input-enable: true
77      output-high: true
78      output-low: true
79
80    required:
81      - pins
82
83    additionalProperties: false
84
85allOf:
86  - $ref: /schemas/pinctrl/qcom,tlmm-common.yaml#
87
88required:
89  - compatible
90  - reg
91
92additionalProperties: false
93
94examples:
95  - |
96    #include <dt-bindings/interrupt-controller/arm-gic.h>
97    msmgpio: pinctrl@fd510000 {
98        compatible = "qcom,msm8226-pinctrl";
99        reg = <0xfd510000 0x4000>;
100
101        gpio-controller;
102        #gpio-cells = <2>;
103        gpio-ranges = <&msmgpio 0 0 117>;
104        interrupt-controller;
105        #interrupt-cells = <2>;
106        interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
107
108        serial-state {
109            pins = "gpio8", "gpio9";
110            function = "blsp_uart3";
111            drive-strength = <8>;
112            bias-disable;
113        };
114    };
115