xref: /linux/Documentation/devicetree/bindings/pinctrl/qcom,ipq8064-pinctrl.yaml (revision c532de5a67a70f8533d495f8f2aaa9a0491c3ad0) 
1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/pinctrl/qcom,ipq8064-pinctrl.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Qualcomm Technologies, Inc. IPQ8064 TLMM block
8
9maintainers:
10  - Bjorn Andersson <bjorn.andersson@linaro.org>
11
12description: |
13  Top Level Mode Multiplexer pin controller in Qualcomm IPQ8064 SoC.
14
15allOf:
16  - $ref: /schemas/pinctrl/qcom,tlmm-common.yaml#
17
18properties:
19  compatible:
20    const: qcom,ipq8064-pinctrl
21
22  reg:
23    maxItems: 1
24
25  interrupts:
26    maxItems: 1
27
28  gpio-reserved-ranges: true
29
30patternProperties:
31  "-state$":
32    oneOf:
33      - $ref: "#/$defs/qcom-ipq8064-tlmm-state"
34      - patternProperties:
35          "-pins$":
36            $ref: "#/$defs/qcom-ipq8064-tlmm-state"
37        additionalProperties: false
38
39$defs:
40  qcom-ipq8064-tlmm-state:
41    type: object
42    description:
43      Pinctrl node's client devices use subnodes for desired pin configuration.
44      Client device subnodes use below standard properties.
45    $ref: qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state
46    unevaluatedProperties: false
47
48    properties:
49      pins:
50        description:
51          List of gpio pins affected by the properties specified in this
52          subnode.
53        items:
54          oneOf:
55            - pattern: "^gpio([0-9]|[1-5][0-9]|6[0-8])$"
56            - enum: [ sdc3_clk, sdc3_cmd, sdc3_data ]
57        minItems: 1
58        maxItems: 36
59
60      function:
61        description:
62          Specify the alternative function to be configured for the specified
63          pins.
64        enum: [ mdio, mi2s, pdm, ssbi, spmi, audio_pcm, gpio, gsbi1, gsbi2, gsbi4, gsbi5,
65                gsbi5_spi_cs1, gsbi5_spi_cs2, gsbi5_spi_cs3, gsbi6, gsbi7, nss_spi, sdc1,
66                spdif, nand, tsif1, tsif2, usb_fs_n, usb_fs, usb2_hsic, rgmii2, sata,
67                pcie1_rst, pcie1_prsnt, pcie1_pwren_n, pcie1_pwren, pcie1_pwrflt,
68                pcie1_clk_req, pcie2_rst, pcie2_prsnt, pcie2_pwren_n, pcie2_pwren,
69                pcie2_pwrflt, pcie2_clk_req, pcie3_rst, pcie3_prsnt, pcie3_pwren_n,
70                pcie3_pwren, pcie3_pwrflt, pcie3_clk_req, ps_hold ]
71
72    required:
73      - pins
74
75required:
76  - compatible
77  - reg
78
79unevaluatedProperties: false
80
81examples:
82  - |
83    #include <dt-bindings/interrupt-controller/arm-gic.h>
84    tlmm: pinctrl@800000 {
85        compatible = "qcom,ipq8064-pinctrl";
86        reg = <0x00800000 0x4000>;
87
88        gpio-controller;
89        #gpio-cells = <2>;
90        gpio-ranges = <&tlmm 0 0 69>;
91        interrupt-controller;
92        #interrupt-cells = <2>;
93        interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
94
95        uart-state {
96            rx-pins {
97                pins = "gpio19";
98                function = "gsbi5";
99                bias-pull-up;
100            };
101
102            tx-pins {
103                pins = "gpio18";
104                function = "gsbi5";
105                bias-disable;
106            };
107        };
108    };
109