xref: /linux/Documentation/devicetree/bindings/pinctrl/qcom,x1e80100-tlmm.yaml (revision 7e47d9d3750c17bdbbcbeac65f6ca54d633a58b5) 
1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/pinctrl/qcom,x1e80100-tlmm.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Qualcomm Technologies, Inc. X1E80100 TLMM block
8
9maintainers:
10  - Rajendra Nayak <quic_rjendra@quicinc.com>
11
12description:
13  Top Level Mode Multiplexer pin controller in Qualcomm X1E80100 SoC.
14
15allOf:
16  - $ref: /schemas/pinctrl/qcom,tlmm-common.yaml#
17
18properties:
19  compatible:
20    const: qcom,x1e80100-tlmm
21
22  reg:
23    maxItems: 1
24
25  interrupts:
26    maxItems: 1
27
28  interrupt-controller: true
29  "#interrupt-cells": true
30  gpio-controller: true
31
32  gpio-reserved-ranges:
33    minItems: 1
34    maxItems: 119
35
36  gpio-line-names:
37    maxItems: 238
38
39  "#gpio-cells": true
40  gpio-ranges: true
41  wakeup-parent: true
42
43patternProperties:
44  "-state$":
45    oneOf:
46      - $ref: "#/$defs/qcom-x1e80100-tlmm-state"
47      - patternProperties:
48          "-pins$":
49            $ref: "#/$defs/qcom-x1e80100-tlmm-state"
50        additionalProperties: false
51
52$defs:
53  qcom-x1e80100-tlmm-state:
54    type: object
55    description:
56      Pinctrl node's client devices use subnodes for desired pin configuration.
57      Client device subnodes use below standard properties.
58    $ref: qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state
59    unevaluatedProperties: false
60
61    properties:
62      pins:
63        description:
64          List of gpio pins affected by the properties specified in this
65          subnode.
66        items:
67          oneOf:
68            - pattern: "^gpio([0-9]|[1-9][0-9]|1[0-9][0-9]|2[0-2][0-9]|23[0-7])$"
69            - enum: [ ufs_reset, sdc2_clk, sdc2_cmd, sdc2_data ]
70        minItems: 1
71        maxItems: 36
72
73      function:
74        description:
75          Specify the alternative function to be configured for the specified
76          pins.
77        enum: [ aon_cci, aoss_cti, atest_char, atest_char0,
78                atest_char1, atest_char2, atest_char3, atest_usb,
79                audio_ext, audio_ref, cam_aon, cam_mclk, cci_async,
80                cci_i2c, cci_timer0, cci_timer1, cci_timer2, cci_timer3,
81                cci_timer4, cmu_rng0, cmu_rng1, cmu_rng2, cmu_rng3,
82                cri_trng, dbg_out, ddr_bist, ddr_pxi0, ddr_pxi1,
83                ddr_pxi2, ddr_pxi3, ddr_pxi4, ddr_pxi5, ddr_pxi6, ddr_pxi7,
84                edp0_hot, edp0_lcd, edp1_hot, edp1_lcd, eusb0_ac, eusb1_ac,
85                eusb2_ac, eusb3_ac, eusb5_ac, eusb6_ac, gcc_gp1, gcc_gp2,
86                gcc_gp3, gpio, i2s0_data0, i2s0_data1, i2s0_sck, i2s0_ws, i2s1_data0,
87                i2s1_data1, i2s1_sck, i2s1_ws, ibi_i3c, jitter_bist, mdp_vsync0,
88                mdp_vsync1, mdp_vsync2, mdp_vsync3, mdp_vsync4, mdp_vsync5,
89                mdp_vsync6, mdp_vsync7, mdp_vsync8, pcie3_clk, pcie4_clk,
90                pcie5_clk, pcie6a_clk, pcie6b_clk, phase_flag, pll_bist, pll_clk,
91                prng_rosc0, prng_rosc1, prng_rosc2, prng_rosc3, qdss_cti,
92                qdss_gpio, qspi00, qspi01, qspi02, qspi03, qspi0_clk, qspi0_cs0,
93                qspi0_cs1, qup0_se0, qup0_se1, qup0_se2, qup0_se3, qup0_se4,
94                qup0_se5, qup0_se6, qup0_se7, qup1_se0, qup1_se1, qup1_se2, qup1_se3,
95                qup1_se4, qup1_se5, qup1_se6, qup1_se7, qup2_se0, qup2_se1, qup2_se2,
96                qup2_se3, qup2_se4, qup2_se5, qup2_se6, qup2_se7, sd_write, sdc4_clk,
97                sdc4_cmd, sdc4_data0, sdc4_data1, sdc4_data2, sdc4_data3, sys_throttle,
98                tb_trig, tgu_ch0, tgu_ch1, tgu_ch2, tgu_ch3, tgu_ch4, tgu_ch5,
99                tgu_ch6, tgu_ch7, tmess_prng0, tmess_prng1, tmess_prng2, tmess_prng3,
100                tsense_pwm1, tsense_pwm2, sense_pwm3, tsense_pwm4, usb0_dp, usb0_phy,
101                usb0_sbrx, usb0_sbtx, usb1_dp, usb1_phy, usb1_sbrx, usb1_sbtx,
102                usb2_dp, usb2_phy, usb2_sbrx, usb2_sbtx, vsense_trigger ]
103
104    required:
105      - pins
106
107required:
108  - compatible
109  - reg
110
111additionalProperties: false
112
113examples:
114  - |
115    #include <dt-bindings/interrupt-controller/arm-gic.h>
116    tlmm: pinctrl@f100000 {
117        compatible = "qcom,x1e80100-tlmm";
118        reg = <0x0f100000 0xf00000>;
119        gpio-controller;
120        #gpio-cells = <2>;
121        gpio-ranges = <&tlmm 0 0 239>;
122        interrupt-controller;
123        #interrupt-cells = <2>;
124        interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
125
126        gpio-wo-state {
127            pins = "gpio1";
128            function = "gpio";
129        };
130
131        uart-w-state {
132            rx-pins {
133                pins = "gpio26";
134                function = "qup2_se7";
135                bias-pull-up;
136            };
137
138            tx-pins {
139                pins = "gpio27";
140                function = "qup2_se7";
141                bias-disable;
142            };
143        };
144    };
145...
146