xref: /linux/Documentation/devicetree/bindings/pinctrl/qcom,sm8650-tlmm.yaml (revision d92618caf9d05e78e0f9c4c6ff9201691acfe48c) 
1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/pinctrl/qcom,sm8650-tlmm.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Qualcomm Technologies, Inc. SM8650 TLMM block
8
9maintainers:
10  - Bjorn Andersson <andersson@kernel.org>
11
12description:
13  Top Level Mode Multiplexer pin controller in Qualcomm SM8650 SoC.
14
15allOf:
16  - $ref: /schemas/pinctrl/qcom,tlmm-common.yaml#
17
18properties:
19  compatible:
20    const: qcom,sm8650-tlmm
21
22  reg:
23    maxItems: 1
24
25  interrupts: true
26  interrupt-controller: true
27  "#interrupt-cells": true
28  gpio-controller: true
29
30  gpio-reserved-ranges:
31    minItems: 1
32    maxItems: 105
33
34  gpio-line-names:
35    maxItems: 210
36
37  "#gpio-cells": true
38  gpio-ranges: true
39  wakeup-parent: true
40
41patternProperties:
42  "-state$":
43    oneOf:
44      - $ref: "#/$defs/qcom-sm8650-tlmm-state"
45      - patternProperties:
46          "-pins$":
47            $ref: "#/$defs/qcom-sm8650-tlmm-state"
48        additionalProperties: false
49
50$defs:
51  qcom-sm8650-tlmm-state:
52    type: object
53    description:
54      Pinctrl node's client devices use subnodes for desired pin configuration.
55      Client device subnodes use below standard properties.
56    $ref: qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state
57    unevaluatedProperties: false
58
59    properties:
60      pins:
61        description:
62          List of gpio pins affected by the properties specified in this
63          subnode.
64        items:
65          oneOf:
66            - pattern: "^gpio([0-9]|[1-9][0-9]|1[0-9][0-9]|20[0-9])$"
67            - enum: [ ufs_reset, sdc2_clk, sdc2_cmd, sdc2_data ]
68        minItems: 1
69        maxItems: 36
70
71      function:
72        description:
73          Specify the alternative function to be configured for the specified
74          pins.
75        enum: [ gpio, aoss_cti, atest_char, atest_usb, audio_ext_mclk0,
76                audio_ext_mclk1, audio_ref_clk, cam_aon_mclk2, cam_aon_mclk4,
77                cam_mclk, cci_async_in, cci_i2c_scl, cci_i2c_sda, cci_timer,
78                cmu_rng, coex_uart1_rx, coex_uart1_tx, coex_uart2_rx,
79                coex_uart2_tx, cri_trng, dbg_out_clk, ddr_bist_complete,
80                ddr_bist_fail, ddr_bist_start, ddr_bist_stop, ddr_pxi0,
81                ddr_pxi1, ddr_pxi2, ddr_pxi3, do_not, dp_hot, gcc_gp1,
82                gcc_gp2, gcc_gp3, gnss_adc0, gnss_adc1, i2chub0_se0,
83                i2chub0_se1, i2chub0_se2, i2chub0_se3, i2chub0_se4,
84                i2chub0_se5, i2chub0_se6, i2chub0_se7, i2chub0_se8,
85                i2chub0_se9, i2s0_data0, i2s0_data1, i2s0_sck, i2s0_ws,
86                i2s1_data0, i2s1_data1, i2s1_sck, i2s1_ws, ibi_i3c,
87                jitter_bist, mdp_vsync, mdp_vsync0_out, mdp_vsync1_out,
88                mdp_vsync2_out, mdp_vsync3_out, mdp_vsync_e, nav_gpio0,
89                nav_gpio1, nav_gpio2, nav_gpio3, pcie0_clk_req_n,
90                pcie1_clk_req_n, phase_flag, pll_bist_sync, pll_clk_aux,
91                prng_rosc0, prng_rosc1, prng_rosc2, prng_rosc3, qdss_cti,
92                qdss_gpio, qlink_big_enable, qlink_big_request,
93                qlink_little_enable, qlink_little_request, qlink_wmss,
94                qspi0, qspi1, qspi2, qspi3, qspi_clk, qspi_cs, qup1_se0,
95                qup1_se1, qup1_se2, qup1_se3, qup1_se4, qup1_se5, qup1_se6,
96                qup1_se7, qup2_se0, qup2_se1, qup2_se2, qup2_se3, qup2_se4,
97                qup2_se5, qup2_se6, qup2_se7, sd_write_protect, sdc40, sdc41,
98                sdc42, sdc43, sdc4_clk, sdc4_cmd, tb_trig_sdc2, tb_trig_sdc4,
99                tgu_ch0_trigout, tgu_ch1_trigout, tgu_ch2_trigout,
100                tgu_ch3_trigout, tmess_prng0, tmess_prng1, tmess_prng2,
101                tmess_prng3, tsense_pwm1, tsense_pwm2, tsense_pwm3, uim0_clk,
102                uim0_data, uim0_present, uim0_reset, uim1_clk, uim1_data,
103                uim1_present, uim1_reset, usb1_hs, usb_phy, vfr_0, vfr_1,
104                vsense_trigger_mirnat ]
105
106    required:
107      - pins
108
109required:
110  - compatible
111  - reg
112
113additionalProperties: false
114
115examples:
116  - |
117    #include <dt-bindings/interrupt-controller/arm-gic.h>
118    tlmm: pinctrl@f100000 {
119        compatible = "qcom,sm8650-tlmm";
120        reg = <0x0f100000 0x300000>;
121        gpio-controller;
122        #gpio-cells = <2>;
123        gpio-ranges = <&tlmm 0 0 211>;
124        interrupt-controller;
125        #interrupt-cells = <2>;
126        interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
127
128        gpio-wo-state {
129            pins = "gpio1";
130            function = "gpio";
131        };
132
133        uart-w-state {
134            rx-pins {
135                pins = "gpio60";
136                function = "qup1_se7";
137                bias-pull-up;
138            };
139
140            tx-pins {
141                pins = "gpio61";
142                function = "qup1_se7";
143                bias-disable;
144            };
145        };
146    };
147...
148