xref: /linux/Documentation/devicetree/bindings/pinctrl/qcom,sm8450-tlmm.yaml (revision 50501936288d6a29d7ef78f25d00e33240fad45f)
1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/pinctrl/qcom,sm8450-tlmm.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Qualcomm Technologies, Inc. SM8450 TLMM block
8
9maintainers:
10  - Vinod Koul <vkoul@kernel.org>
11
12description:
13  Top Level Mode Multiplexer pin controller in Qualcomm SM8450 SoC.
14
15allOf:
16  - $ref: /schemas/pinctrl/qcom,tlmm-common.yaml#
17
18properties:
19  compatible:
20    const: qcom,sm8450-tlmm
21
22  reg:
23    maxItems: 1
24
25  interrupts:
26    maxItems: 1
27
28  interrupt-controller: true
29  "#interrupt-cells": true
30  gpio-controller: true
31
32  gpio-reserved-ranges:
33    minItems: 1
34    maxItems: 105
35
36  gpio-line-names:
37    maxItems: 210
38
39  "#gpio-cells": true
40  gpio-ranges: true
41  wakeup-parent: true
42
43required:
44  - compatible
45  - reg
46
47additionalProperties: false
48
49patternProperties:
50  "-state$":
51    oneOf:
52      - $ref: "#/$defs/qcom-sm8450-tlmm-state"
53      - patternProperties:
54          "-pins$":
55            $ref: "#/$defs/qcom-sm8450-tlmm-state"
56        additionalProperties: false
57
58$defs:
59  qcom-sm8450-tlmm-state:
60    type: object
61    description:
62      Pinctrl node's client devices use subnodes for desired pin configuration.
63      Client device subnodes use below standard properties.
64    $ref: qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state
65    unevaluatedProperties: false
66
67    properties:
68      pins:
69        description:
70          List of gpio pins affected by the properties specified in this
71          subnode.
72        items:
73          oneOf:
74            - pattern: "^gpio([0-9]|[1-9][0-9]|1[0-9][0-9]|20[0-9])$"
75            - enum: [ ufs_reset, sdc2_clk, sdc2_cmd, sdc2_data ]
76        minItems: 1
77        maxItems: 36
78
79      function:
80        description:
81          Specify the alternative function to be configured for the specified
82          pins.
83        enum: [ aon_cam, atest_char, atest_usb, audio_ref, cam_mclk, cci_async,
84                cci_i2c, cci_timer, cmu_rng, coex_uart1, coex_uart2, cri_trng,
85                cri_trng0, cri_trng1, dbg_out, ddr_bist, ddr_pxi0, ddr_pxi1,
86                ddr_pxi2, ddr_pxi3, dp_hot, gcc_gp1, gcc_gp2, gcc_gp3,
87                gpio, ibi_i3c, jitter_bist, mdp_vsync, mdp_vsync0, mdp_vsync1,
88                mdp_vsync2, mdp_vsync3, mi2s0_data0, mi2s0_data1, mi2s0_sck,
89                mi2s0_ws, mi2s2_data0, mi2s2_data1, mi2s2_sck, mi2s2_ws,
90                mss_grfc0, mss_grfc1, mss_grfc10, mss_grfc11, mss_grfc12,
91                mss_grfc2, mss_grfc3, mss_grfc4, mss_grfc5, mss_grfc6,
92                mss_grfc7, mss_grfc8, mss_grfc9, nav, pcie0_clkreqn,
93                pcie1_clkreqn, phase_flag, pll_bist, pll_clk, pri_mi2s,
94                prng_rosc, qdss_cti, qdss_gpio, qlink0_enable, qlink0_request,
95                qlink0_wmss, qlink1_enable, qlink1_request, qlink1_wmss,
96                qlink2_enable, qlink2_request, qlink2_wmss, qspi0, qspi1,
97                qspi2, qspi3, qspi_clk, qspi_cs, qup0, qup1, qup10, qup11,
98                qup12, qup13, qup14, qup15, qup16, qup17, qup18, qup19, qup2,
99                qup20, qup21, qup3, qup4, qup5, qup6, qup7, qup8, qup9, qup_l4,
100                qup_l5, qup_l6, sd_write, sdc40, sdc41, sdc42, sdc43, sdc4_clk,
101                sdc4_cmd, sec_mi2s, tb_trig, tgu_ch0, tgu_ch1, tgu_ch2,
102                tgu_ch3, tmess_prng0, tmess_prng1, tmess_prng2, tmess_prng3,
103                tsense_pwm1, tsense_pwm2, uim0_clk, uim0_data, uim0_present,
104                uim0_reset, uim1_clk, uim1_data, uim1_present, uim1_reset,
105                usb2phy_ac, usb_phy, vfr_0, vfr_1, vsense_trigger ]
106
107    required:
108      - pins
109
110examples:
111  - |
112    #include <dt-bindings/interrupt-controller/arm-gic.h>
113    pinctrl@f100000 {
114        compatible = "qcom,sm8450-tlmm";
115        reg = <0x0f100000 0x300000>;
116        gpio-controller;
117        #gpio-cells = <2>;
118        gpio-ranges = <&tlmm 0 0 211>;
119        interrupt-controller;
120        #interrupt-cells = <2>;
121        interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
122
123        gpio-wo-state {
124            pins = "gpio1";
125            function = "gpio";
126        };
127
128        uart-w-state {
129            rx-pins {
130                pins = "gpio26";
131                function = "qup7";
132                bias-pull-up;
133            };
134
135            tx-pins {
136                pins = "gpio27";
137                function = "qup7";
138                bias-disable;
139            };
140        };
141    };
142...
143