1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2%YAML 1.2 3--- 4$id: http://devicetree.org/schemas/pinctrl/qcom,sm6115-tlmm.yaml# 5$schema: http://devicetree.org/meta-schemas/core.yaml# 6 7title: Qualcomm Technologies, Inc. SM6115, SM4250 TLMM block 8 9maintainers: 10 - Iskren Chernev <iskren.chernev@gmail.com> 11 12description: 13 Top Level Mode Multiplexer pin controller in Qualcomm SM4250 and SM6115 14 SoCs. 15 16properties: 17 compatible: 18 const: qcom,sm6115-tlmm 19 20 reg: 21 minItems: 3 22 maxItems: 3 23 24 reg-names: 25 items: 26 - const: west 27 - const: south 28 - const: east 29 30 interrupts: true 31 interrupt-controller: true 32 "#interrupt-cells": true 33 gpio-controller: true 34 "#gpio-cells": true 35 gpio-ranges: true 36 gpio-reserved-ranges: true 37 wakeup-parent: true 38 39patternProperties: 40 "-state$": 41 oneOf: 42 - $ref: "#/$defs/qcom-sm6115-tlmm-state" 43 - patternProperties: 44 "-pins$": 45 $ref: "#/$defs/qcom-sm6115-tlmm-state" 46 additionalProperties: false 47 48$defs: 49 qcom-sm6115-tlmm-state: 50 type: object 51 description: 52 Pinctrl node's client devices use subnodes for desired pin configuration. 53 Client device subnodes use below standard properties. 54 $ref: qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state 55 56 properties: 57 pins: 58 description: 59 List of gpio pins affected by the properties specified in this 60 subnode. 61 items: 62 oneOf: 63 - pattern: "^gpio([0-9]|[1-9][0-9]|10[0-9]|11[0-2])$" 64 - enum: [ sdc1_rclk, sdc1_clk, sdc1_cmd, sdc1_data, 65 sdc2_clk, sdc2_cmd, sdc2_data, ufs_reset ] 66 minItems: 1 67 maxItems: 36 68 69 function: 70 description: 71 Specify the alternative function to be configured for the specified 72 pins. 73 74 enum: [ adsp_ext, agera_pll, atest, cam_mclk, cci_async, cci_i2c, 75 cci_timer, cri_trng, dac_calib, dbg_out, ddr_bist, ddr_pxi0, 76 ddr_pxi1, ddr_pxi2, ddr_pxi3, gcc_gp1, gcc_gp2, gcc_gp3, gpio, 77 gp_pdm0, gp_pdm1, gp_pdm2, gsm0_tx, gsm1_tx, jitter_bist, 78 mdp_vsync, mdp_vsync_out_0, mdp_vsync_out_1, mpm_pwr, mss_lte, 79 m_voc, nav_gpio, pa_indicator, pbs, pbs_out, phase_flag, 80 pll_bist, pll_bypassnl, pll_reset, prng_rosc, qdss_cti, 81 qdss_gpio, qup0, qup1, qup2, qup3, qup4, qup5, sdc1_tb, 82 sdc2_tb, sd_write, ssbi_wtr1, tgu, tsense_pwm, uim1_clk, 83 uim1_data, uim1_present, uim1_reset, uim2_clk, uim2_data, 84 uim2_present, uim2_reset, usb_phy, vfr_1, vsense_trigger, 85 wlan1_adc0, elan1_adc1 ] 86 87 bias-pull-down: true 88 bias-pull-up: true 89 bias-disable: true 90 drive-strength: true 91 output-high: true 92 output-low: true 93 94 required: 95 - pins 96 97 additionalProperties: false 98 99allOf: 100 - $ref: /schemas/pinctrl/qcom,tlmm-common.yaml# 101 102required: 103 - compatible 104 - reg 105 - reg-names 106 107additionalProperties: false 108 109examples: 110 - | 111 #include <dt-bindings/interrupt-controller/arm-gic.h> 112 tlmm: pinctrl@500000 { 113 compatible = "qcom,sm6115-tlmm"; 114 reg = <0x500000 0x400000>, 115 <0x900000 0x400000>, 116 <0xd00000 0x400000>; 117 reg-names = "west", "south", "east"; 118 interrupts = <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH>; 119 gpio-controller; 120 #gpio-cells = <2>; 121 interrupt-controller; 122 #interrupt-cells = <2>; 123 gpio-ranges = <&tlmm 0 0 114>; 124 125 sdc2_on_state: sdc2-on-state { 126 clk-pins { 127 pins = "sdc2_clk"; 128 bias-disable; 129 drive-strength = <16>; 130 }; 131 132 cmd-pins { 133 pins = "sdc2_cmd"; 134 bias-pull-up; 135 drive-strength = <10>; 136 }; 137 138 data-pins { 139 pins = "sdc2_data"; 140 bias-pull-up; 141 drive-strength = <10>; 142 }; 143 144 sd-cd-pins { 145 pins = "gpio88"; 146 function = "gpio"; 147 bias-pull-up; 148 drive-strength = <2>; 149 }; 150 }; 151 }; 152