xref: /linux/Documentation/devicetree/bindings/pinctrl/qcom,sm6115-tlmm.yaml (revision 0d8eae7b124e2ddaee00f186fe922450faad0ed7) 
1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/pinctrl/qcom,sm6115-tlmm.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Qualcomm Technologies, Inc. SM6115, SM4250 TLMM block
8
9maintainers:
10  - Iskren Chernev <iskren.chernev@gmail.com>
11
12description:
13  Top Level Mode Multiplexer pin controller in Qualcomm SM4250 and SM6115
14  SoCs.
15
16properties:
17  compatible:
18    const: qcom,sm6115-tlmm
19
20  reg:
21    maxItems: 3
22
23  reg-names:
24    items:
25      - const: west
26      - const: south
27      - const: east
28
29  interrupts: true
30  interrupt-controller: true
31  "#interrupt-cells": true
32  gpio-controller: true
33  "#gpio-cells": true
34  gpio-ranges: true
35  gpio-reserved-ranges: true
36  wakeup-parent: true
37
38patternProperties:
39  "-state$":
40    oneOf:
41      - $ref: "#/$defs/qcom-sm6115-tlmm-state"
42      - patternProperties:
43          "-pins$":
44            $ref: "#/$defs/qcom-sm6115-tlmm-state"
45        additionalProperties: false
46
47$defs:
48  qcom-sm6115-tlmm-state:
49    type: object
50    description:
51      Pinctrl node's client devices use subnodes for desired pin configuration.
52      Client device subnodes use below standard properties.
53    $ref: qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state
54
55    properties:
56      pins:
57        description:
58          List of gpio pins affected by the properties specified in this
59          subnode.
60        items:
61          oneOf:
62            - pattern: "^gpio([0-9]|[1-9][0-9]|10[0-9]|11[0-2])$"
63            - enum: [ sdc1_rclk, sdc1_clk, sdc1_cmd, sdc1_data,
64                      sdc2_clk, sdc2_cmd, sdc2_data, ufs_reset ]
65        minItems: 1
66        maxItems: 36
67
68      function:
69        description:
70          Specify the alternative function to be configured for the specified
71          pins.
72
73        enum: [ adsp_ext, agera_pll, atest, cam_mclk, cci_async, cci_i2c,
74                cci_timer, cri_trng, dac_calib, dbg_out, ddr_bist, ddr_pxi0,
75                ddr_pxi1, ddr_pxi2, ddr_pxi3, gcc_gp1, gcc_gp2, gcc_gp3, gpio,
76                gp_pdm0, gp_pdm1, gp_pdm2, gsm0_tx, gsm1_tx, jitter_bist,
77                mdp_vsync, mdp_vsync_out_0, mdp_vsync_out_1, mpm_pwr, mss_lte,
78                m_voc, nav_gpio, pa_indicator, pbs, pbs_out, phase_flag,
79                pll_bist, pll_bypassnl, pll_reset, prng_rosc, qdss_cti,
80                qdss_gpio, qup0, qup1, qup2, qup3, qup4, qup5, sdc1_tb,
81                sdc2_tb, sd_write, ssbi_wtr1, tgu, tsense_pwm, uim1_clk,
82                uim1_data, uim1_present, uim1_reset, uim2_clk, uim2_data,
83                uim2_present, uim2_reset, usb_phy, vfr_1, vsense_trigger,
84                wlan1_adc0, elan1_adc1 ]
85
86      bias-pull-down: true
87      bias-pull-up: true
88      bias-disable: true
89      drive-strength: true
90      output-high: true
91      output-low: true
92
93    required:
94      - pins
95
96    additionalProperties: false
97
98allOf:
99  - $ref: /schemas/pinctrl/qcom,tlmm-common.yaml#
100
101required:
102  - compatible
103  - reg
104  - reg-names
105
106additionalProperties: false
107
108examples:
109  - |
110    #include <dt-bindings/interrupt-controller/arm-gic.h>
111    tlmm: pinctrl@500000 {
112        compatible = "qcom,sm6115-tlmm";
113        reg = <0x500000 0x400000>,
114              <0x900000 0x400000>,
115              <0xd00000 0x400000>;
116        reg-names = "west", "south", "east";
117        interrupts = <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH>;
118        gpio-controller;
119        #gpio-cells = <2>;
120        interrupt-controller;
121        #interrupt-cells = <2>;
122        gpio-ranges = <&tlmm 0 0 114>;
123
124        sdc2_on_state: sdc2-on-state {
125            clk-pins {
126                pins = "sdc2_clk";
127                bias-disable;
128                drive-strength = <16>;
129            };
130
131            cmd-pins {
132                pins = "sdc2_cmd";
133                bias-pull-up;
134                drive-strength = <10>;
135            };
136
137            data-pins {
138                pins = "sdc2_data";
139                bias-pull-up;
140                drive-strength = <10>;
141            };
142
143            sd-cd-pins {
144                pins = "gpio88";
145                function = "gpio";
146                bias-pull-up;
147                drive-strength = <2>;
148            };
149        };
150    };
151