xref: /linux/Documentation/devicetree/bindings/pinctrl/qcom,sdx75-tlmm.yaml (revision 8c0aa95bd0f885a9d87819e02bd28bc03630189d) 
1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/pinctrl/qcom,sdx75-tlmm.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Qualcomm Technologies, Inc. SDX75 TLMM block
8
9maintainers:
10  - Rohit Agarwal <quic_rohiagar@quicinc.com>
11
12description:
13  Top Level Mode Multiplexer pin controller in Qualcomm SDX75 SoC.
14
15allOf:
16  - $ref: /schemas/pinctrl/qcom,tlmm-common.yaml#
17
18properties:
19  compatible:
20    const: qcom,sdx75-tlmm
21
22  reg:
23    maxItems: 1
24
25  interrupts:
26    maxItems: 1
27
28  interrupt-controller: true
29  "#interrupt-cells": true
30  gpio-controller: true
31
32  gpio-reserved-ranges:
33    minItems: 1
34    maxItems: 67
35
36  gpio-line-names:
37    maxItems: 133
38
39  "#gpio-cells": true
40  gpio-ranges: true
41  wakeup-parent: true
42
43patternProperties:
44  "-state$":
45    oneOf:
46      - $ref: "#/$defs/qcom-sdx75-tlmm-state"
47      - patternProperties:
48          "-pins$":
49            $ref: "#/$defs/qcom-sdx75-tlmm-state"
50        additionalProperties: false
51
52$defs:
53  qcom-sdx75-tlmm-state:
54    type: object
55    description:
56      Pinctrl node's client devices use subnodes for desired pin configuration.
57      Client device subnodes use below standard properties.
58    $ref: qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state
59    unevaluatedProperties: false
60
61    properties:
62      pins:
63        description:
64          List of gpio pins affected by the properties specified in this
65          subnode.
66        items:
67          oneOf:
68            - pattern: "^gpio([0-9]|[1-9][0-9]|1[0-2][0-9]|13[0-2])$"
69            - enum: [ sdc1_clk, sdc1_cmd, sdc1_data, sdc1_rclk, sdc2_clk, sdc2_cmd, sdc2_data ]
70        minItems: 1
71        maxItems: 36
72
73      function:
74        description:
75          Specify the alternative function to be configured for the specified
76          pins.
77        enum: [ adsp_ext, atest_char, audio_ref_clk, bimc_dte, char_exec, coex_uart2,
78                coex_uart, cri_trng, cri_trng0, cri_trng1, dbg_out_clk, ddr_bist,
79                ddr_pxi0, ebi0_wrcdc, ebi2_a, ebi2_lcd, ebi2_lcd_te, emac0_mcg,
80                emac0_ptp, emac1_mcg, emac1_ptp, emac_cdc, emac_pps_in, eth0_mdc,
81                eth0_mdio, eth1_mdc, eth1_mdio, ext_dbg, gcc_125_clk, gcc_gp1_clk,
82                gcc_gp2_clk, gcc_gp3_clk, gcc_plltest, gpio, i2s_mclk, jitter_bist,
83                ldo_en, ldo_update, m_voc, mgpi_clk, native_char, native_tsens,
84                native_tsense, nav_dr_sync, nav_gpio, pa_indicator, pci_e,
85                pcie0_clkreq_n, pcie1_clkreq_n, pcie2_clkreq_n, pll_bist_sync,
86                pll_clk_aux, pll_ref_clk, pri_mi2s, prng_rosc, qdss_cti, qdss_gpio,
87                qlink0_b_en, qlink0_b_req, qlink0_l_en, qlink0_l_req, qlink0_wmss,
88                qlink1_l_en, qlink1_l_req, qlink1_wmss, qup_se0, qup_se1_l2_mira,
89                qup_se1_l2_mirb, qup_se1_l3_mira, qup_se1_l3_mirb, qup_se2, qup_se3,
90                qup_se4, qup_se5, qup_se6, qup_se7, qup_se8, rgmii_rx_ctl, rgmii_rxc,
91                rgmii_rxd, rgmii_tx_ctl, rgmii_txc, rgmii_txd, sd_card, sdc1_tb,
92                sdc2_tb_trig, sec_mi2s, sgmii_phy_intr0_n, sgmii_phy_intr1_n,
93                spmi_coex, spmi_vgi, tgu_ch0_trigout, tmess_prng0, tmess_prng1,
94                tmess_prng2, tmess_prng3, tri_mi2s, uim1_clk, uim1_data, uim1_present,
95                uim1_reset, uim2_clk, uim2_data, uim2_present, uim2_reset,
96                usb2phy_ac_en, vsense_trigger_mirnat]
97
98    required:
99      - pins
100
101required:
102  - compatible
103  - reg
104
105additionalProperties: false
106
107examples:
108  - |
109    #include <dt-bindings/interrupt-controller/arm-gic.h>
110    tlmm: pinctrl@f100000 {
111        compatible = "qcom,sdx75-tlmm";
112        reg = <0x0f100000 0x300000>;
113        gpio-controller;
114        #gpio-cells = <2>;
115        gpio-ranges = <&tlmm 0 0 133>;
116        interrupt-controller;
117        #interrupt-cells = <2>;
118        interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
119
120        gpio-wo-state {
121            pins = "gpio1";
122            function = "gpio";
123        };
124
125        uart-w-state {
126            rx-pins {
127                pins = "gpio12";
128                function = "qup_se1_l2_mira";
129                bias-disable;
130            };
131
132            tx-pins {
133                pins = "gpio13";
134                function = "qup_se1_l3_mira";
135                bias-disable;
136            };
137        };
138    };
139...
140