1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2%YAML 1.2 3--- 4$id: http://devicetree.org/schemas/pinctrl/qcom,sdx75-tlmm.yaml# 5$schema: http://devicetree.org/meta-schemas/core.yaml# 6 7title: Qualcomm Technologies, Inc. SDX75 TLMM block 8 9maintainers: 10 - Rohit Agarwal <quic_rohiagar@quicinc.com> 11 12description: 13 Top Level Mode Multiplexer pin controller in Qualcomm SDX75 SoC. 14 15allOf: 16 - $ref: /schemas/pinctrl/qcom,tlmm-common.yaml# 17 18properties: 19 compatible: 20 const: qcom,sdx75-tlmm 21 22 reg: 23 maxItems: 1 24 25 interrupts: true 26 interrupt-controller: true 27 "#interrupt-cells": true 28 gpio-controller: true 29 30 gpio-reserved-ranges: 31 minItems: 1 32 maxItems: 67 33 34 gpio-line-names: 35 maxItems: 133 36 37 "#gpio-cells": true 38 gpio-ranges: true 39 wakeup-parent: true 40 41patternProperties: 42 "-state$": 43 oneOf: 44 - $ref: "#/$defs/qcom-sdx75-tlmm-state" 45 - patternProperties: 46 "-pins$": 47 $ref: "#/$defs/qcom-sdx75-tlmm-state" 48 additionalProperties: false 49 50$defs: 51 qcom-sdx75-tlmm-state: 52 type: object 53 description: 54 Pinctrl node's client devices use subnodes for desired pin configuration. 55 Client device subnodes use below standard properties. 56 $ref: qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state 57 unevaluatedProperties: false 58 59 properties: 60 pins: 61 description: 62 List of gpio pins affected by the properties specified in this 63 subnode. 64 items: 65 oneOf: 66 - pattern: "^gpio([0-9]|[1-9][0-9]|1[0-2][0-9]|13[0-2])$" 67 - enum: [ sdc1_clk, sdc1_cmd, sdc1_data, sdc1_rclk, sdc2_clk, sdc2_cmd, sdc2_data ] 68 minItems: 1 69 maxItems: 36 70 71 function: 72 description: 73 Specify the alternative function to be configured for the specified 74 pins. 75 enum: [ adsp_ext, atest_char, audio_ref_clk, bimc_dte, char_exec, coex_uart2, 76 coex_uart, cri_trng, cri_trng0, cri_trng1, dbg_out_clk, ddr_bist, 77 ddr_pxi0, ebi0_wrcdc, ebi2_a, ebi2_lcd, ebi2_lcd_te, emac0_mcg, 78 emac0_ptp, emac1_mcg, emac1_ptp, emac_cdc, emac_pps_in, eth0_mdc, 79 eth0_mdio, eth1_mdc, eth1_mdio, ext_dbg, gcc_125_clk, gcc_gp1_clk, 80 gcc_gp2_clk, gcc_gp3_clk, gcc_plltest, gpio, i2s_mclk, jitter_bist, 81 ldo_en, ldo_update, m_voc, mgpi_clk, native_char, native_tsens, 82 native_tsense, nav_dr_sync, nav_gpio, pa_indicator, pci_e, 83 pcie0_clkreq_n, pcie1_clkreq_n, pcie2_clkreq_n, pll_bist_sync, 84 pll_clk_aux, pll_ref_clk, pri_mi2s, prng_rosc, qdss_cti, qdss_gpio, 85 qlink0_b_en, qlink0_b_req, qlink0_l_en, qlink0_l_req, qlink0_wmss, 86 qlink1_l_en, qlink1_l_req, qlink1_wmss, qup_se0, qup_se1_l2_mira, 87 qup_se1_l2_mirb, qup_se1_l3_mira, qup_se1_l3_mirb, qup_se2, qup_se3, 88 qup_se4, qup_se5, qup_se6, qup_se7, qup_se8, rgmii_rx_ctl, rgmii_rxc, 89 rgmii_rxd, rgmii_tx_ctl, rgmii_txc, rgmii_txd, sd_card, sdc1_tb, 90 sdc2_tb_trig, sec_mi2s, sgmii_phy_intr0_n, sgmii_phy_intr1_n, 91 spmi_coex, spmi_vgi, tgu_ch0_trigout, tmess_prng0, tmess_prng1, 92 tmess_prng2, tmess_prng3, tri_mi2s, uim1_clk, uim1_data, uim1_present, 93 uim1_reset, uim2_clk, uim2_data, uim2_present, uim2_reset, 94 usb2phy_ac_en, vsense_trigger_mirnat] 95 96 required: 97 - pins 98 99required: 100 - compatible 101 - reg 102 103additionalProperties: false 104 105examples: 106 - | 107 #include <dt-bindings/interrupt-controller/arm-gic.h> 108 tlmm: pinctrl@f100000 { 109 compatible = "qcom,sdx75-tlmm"; 110 reg = <0x0f100000 0x300000>; 111 gpio-controller; 112 #gpio-cells = <2>; 113 gpio-ranges = <&tlmm 0 0 133>; 114 interrupt-controller; 115 #interrupt-cells = <2>; 116 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; 117 118 gpio-wo-state { 119 pins = "gpio1"; 120 function = "gpio"; 121 }; 122 123 uart-w-state { 124 rx-pins { 125 pins = "gpio12"; 126 function = "qup_se1_l2_mira"; 127 bias-disable; 128 }; 129 130 tx-pins { 131 pins = "gpio13"; 132 function = "qup_se1_l3_mira"; 133 bias-disable; 134 }; 135 }; 136 }; 137... 138