xref: /linux/Documentation/devicetree/bindings/pinctrl/qcom,sc8280xp-tlmm.yaml (revision 2f98e686ef59b5d19af5847d755798e2031bee3a) 
1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/pinctrl/qcom,sc8280xp-tlmm.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Qualcomm Technologies, Inc. SC8280XP TLMM block
8
9maintainers:
10  - Bjorn Andersson <bjorn.andersson@linaro.org>
11
12description: |
13  Top Level Mode Multiplexer pin controller in Qualcomm SC8280XP SoC.
14
15allOf:
16  - $ref: /schemas/pinctrl/qcom,tlmm-common.yaml#
17
18properties:
19  compatible:
20    const: qcom,sc8280xp-tlmm
21
22  reg:
23    maxItems: 1
24
25  interrupts:
26    maxItems: 1
27
28  interrupt-controller: true
29  "#interrupt-cells": true
30  gpio-controller: true
31  gpio-reserved-ranges: true
32  "#gpio-cells": true
33  gpio-ranges: true
34  wakeup-parent: true
35
36required:
37  - compatible
38  - reg
39
40additionalProperties: false
41
42patternProperties:
43  "-state$":
44    oneOf:
45      - $ref: "#/$defs/qcom-sc8280xp-tlmm-state"
46      - patternProperties:
47          "-pins$":
48            $ref: "#/$defs/qcom-sc8280xp-tlmm-state"
49        additionalProperties: false
50
51$defs:
52  qcom-sc8280xp-tlmm-state:
53    type: object
54    description:
55      Pinctrl node's client devices use subnodes for desired pin configuration.
56      Client device subnodes use below standard properties.
57    $ref: qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state
58    unevaluatedProperties: false
59
60    properties:
61      pins:
62        description:
63          List of gpio pins affected by the properties specified in this
64          subnode.
65        items:
66          oneOf:
67            - pattern: "^gpio([0-9]|[1-9][0-9]|1[0-9][0-9]|2[0-1][0-9]|22[0-7])$"
68            - enum: [ sdc2_clk, sdc2_cmd, sdc2_data, ufs_reset, ufs1_reset ]
69        minItems: 1
70        maxItems: 16
71
72      function:
73        description:
74          Specify the alternative function to be configured for the specified
75          pins.
76
77        enum: [ atest_char, atest_usb, audio_ref, cam_mclk, cci_async, cci_i2c,
78                cci_timer0, cci_timer1, cci_timer2, cci_timer3, cci_timer4,
79                cci_timer5, cci_timer6, cci_timer7, cci_timer8, cci_timer9,
80                cmu_rng, cri_trng, cri_trng0, cri_trng1, dbg_out, ddr_bist,
81                ddr_pxi0, ddr_pxi1, ddr_pxi2, ddr_pxi3, ddr_pxi4, ddr_pxi5,
82                ddr_pxi6, ddr_pxi7, dp2_hot, dp3_hot, edp0_lcd, edp1_lcd,
83                edp2_lcd, edp3_lcd, edp_hot, emac0_dll, emac0_mcg0, emac0_mcg1,
84                emac0_mcg2, emac0_mcg3, emac0_phy, emac0_ptp, emac1_dll0,
85                emac1_dll1, emac1_mcg0, emac1_mcg1, emac1_mcg2, emac1_mcg3,
86                emac1_phy, emac1_ptp, gcc_gp1, gcc_gp2, gcc_gp3, gcc_gp4,
87                gcc_gp5, gpio, hs1_mi2s, hs2_mi2s, hs3_mi2s, ibi_i3c,
88                jitter_bist, lpass_slimbus, mdp0_vsync0, mdp0_vsync1,
89                mdp0_vsync2, mdp0_vsync3, mdp0_vsync4, mdp0_vsync5,
90                mdp0_vsync6, mdp0_vsync7, mdp0_vsync8, mdp1_vsync0,
91                mdp1_vsync1, mdp1_vsync2, mdp1_vsync3, mdp1_vsync4,
92                mdp1_vsync5, mdp1_vsync6, mdp1_vsync7, mdp1_vsync8, mdp_vsync,
93                mi2s0_data0, mi2s0_data1, mi2s0_sck, mi2s0_ws, mi2s1_data0,
94                mi2s1_data1, mi2s1_sck, mi2s1_ws, mi2s2_data0, mi2s2_data1,
95                mi2s2_sck, mi2s2_ws, mi2s_mclk1, mi2s_mclk2, pcie2a_clkreq,
96                pcie2b_clkreq, pcie3a_clkreq, pcie3b_clkreq, pcie4_clkreq,
97                phase_flag, pll_bist, pll_clk, prng_rosc0, prng_rosc1,
98                prng_rosc2, prng_rosc3, qdss_cti, qdss_gpio, qspi, qspi_clk,
99                qspi_cs, qup0, qup1, qup2, qup3, qup4, qup5, qup6, qup7, qup8,
100                qup9, qup10, qup11, qup12, qup13, qup14, qup15, qup16, qup17,
101                qup18, qup19, qup20, qup21, qup22, qup23, rgmii_0, rgmii_1,
102                sd_write, sdc40, sdc42, sdc43, sdc4_clk, sdc4_cmd, tb_trig,
103                tgu, tsense_pwm1, tsense_pwm2, tsense_pwm3, tsense_pwm4,
104                usb0_dp, usb0_phy, usb0_sbrx, usb0_sbtx, usb0_usb4, usb1_dp,
105                usb1_phy, usb1_sbrx, usb1_sbtx, usb1_usb4, usb2phy_ac,
106                vsense_trigger ]
107
108    required:
109      - pins
110
111examples:
112  - |
113    #include <dt-bindings/interrupt-controller/arm-gic.h>
114    pinctrl@f100000 {
115        compatible = "qcom,sc8280xp-tlmm";
116        reg = <0x0f100000 0x300000>;
117        interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
118        gpio-controller;
119        #gpio-cells = <2>;
120        interrupt-controller;
121        #interrupt-cells = <2>;
122        gpio-ranges = <&tlmm 0 0 230>;
123
124        gpio-wo-subnode-state {
125            pins = "gpio1";
126            function = "gpio";
127        };
128
129        uart-w-subnodes-state {
130            rx-pins {
131                pins = "gpio4";
132                function = "qup14";
133                bias-pull-up;
134            };
135
136            tx-pins {
137                pins = "gpio5";
138                function = "qup14";
139                bias-disable;
140            };
141        };
142    };
143...
144