xref: /linux/Documentation/devicetree/bindings/pinctrl/qcom,sc8280xp-tlmm.yaml (revision 79d770afa0d582956bc2cb577fc9e3b413702ab8)

# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/pinctrl/qcom,sc8280xp-tlmm.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Qualcomm Technologies, Inc. SC8280XP TLMM block

maintainers:
  - Bjorn Andersson <bjorn.andersson@linaro.org>

description: |
  Top Level Mode Multiplexer pin controller in Qualcomm SC8280XP SoC.

allOf:
  - $ref: /schemas/pinctrl/qcom,tlmm-common.yaml#

properties:
  compatible:
    const: qcom,sc8280xp-tlmm

  reg:
    maxItems: 1

  interrupts:
    maxItems: 1

  gpio-reserved-ranges: true

patternProperties:
  "-state$":
    oneOf:
      - $ref: "#/$defs/qcom-sc8280xp-tlmm-state"
      - patternProperties:
          "-pins$":
            $ref: "#/$defs/qcom-sc8280xp-tlmm-state"
        additionalProperties: false

$defs:
  qcom-sc8280xp-tlmm-state:
    type: object
    description:
      Pinctrl node's client devices use subnodes for desired pin configuration.
      Client device subnodes use below standard properties.
    $ref: qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state
    unevaluatedProperties: false

    properties:
      pins:
        description:
          List of gpio pins affected by the properties specified in this
          subnode.
        items:
          oneOf:
            - pattern: "^gpio([0-9]|[1-9][0-9]|1[0-9][0-9]|2[0-1][0-9]|22[0-7])$"
            - enum: [ sdc2_clk, sdc2_cmd, sdc2_data, ufs_reset, ufs1_reset ]
        minItems: 1
        maxItems: 16

      function:
        description:
          Specify the alternative function to be configured for the specified
          pins.

        enum: [ atest_char, atest_usb, audio_ref, cam_mclk, cci_async, cci_i2c,
                cci_timer0, cci_timer1, cci_timer2, cci_timer3, cci_timer4,
                cci_timer5, cci_timer6, cci_timer7, cci_timer8, cci_timer9,
                cmu_rng, cri_trng, cri_trng0, cri_trng1, dbg_out, ddr_bist,
                ddr_pxi0, ddr_pxi1, ddr_pxi2, ddr_pxi3, ddr_pxi4, ddr_pxi5,
                ddr_pxi6, ddr_pxi7, dp2_hot, dp3_hot, edp0_lcd, edp1_lcd,
                edp2_lcd, edp3_lcd, edp_hot, emac0_dll, emac0_mcg0, emac0_mcg1,
                emac0_mcg2, emac0_mcg3, emac0_phy, emac0_ptp, emac1_dll0,
                emac1_dll1, emac1_mcg0, emac1_mcg1, emac1_mcg2, emac1_mcg3,
                emac1_phy, emac1_ptp, gcc_gp1, gcc_gp2, gcc_gp3, gcc_gp4,
                gcc_gp5, gpio, hs1_mi2s, hs2_mi2s, hs3_mi2s, ibi_i3c,
                jitter_bist, lpass_slimbus, mdp0_vsync0, mdp0_vsync1,
                mdp0_vsync2, mdp0_vsync3, mdp0_vsync4, mdp0_vsync5,
                mdp0_vsync6, mdp0_vsync7, mdp0_vsync8, mdp1_vsync0,
                mdp1_vsync1, mdp1_vsync2, mdp1_vsync3, mdp1_vsync4,
                mdp1_vsync5, mdp1_vsync6, mdp1_vsync7, mdp1_vsync8, mdp_vsync,
                mi2s0_data0, mi2s0_data1, mi2s0_sck, mi2s0_ws, mi2s1_data0,
                mi2s1_data1, mi2s1_sck, mi2s1_ws, mi2s2_data0, mi2s2_data1,
                mi2s2_sck, mi2s2_ws, mi2s_mclk1, mi2s_mclk2, pcie2a_clkreq,
                pcie2b_clkreq, pcie3a_clkreq, pcie3b_clkreq, pcie4_clkreq,
                phase_flag, pll_bist, pll_clk, prng_rosc0, prng_rosc1,
                prng_rosc2, prng_rosc3, qdss_cti, qdss_gpio, qspi, qspi_clk,
                qspi_cs, qup0, qup1, qup2, qup3, qup4, qup5, qup6, qup7, qup8,
                qup9, qup10, qup11, qup12, qup13, qup14, qup15, qup16, qup17,
                qup18, qup19, qup20, qup21, qup22, qup23, rgmii_0, rgmii_1,
                sd_write, sdc40, sdc42, sdc43, sdc4_clk, sdc4_cmd, tb_trig,
                tgu, tsense_pwm1, tsense_pwm2, tsense_pwm3, tsense_pwm4,
                usb0_dp, usb0_phy, usb0_sbrx, usb0_sbtx, usb0_usb4, usb1_dp,
                usb1_phy, usb1_sbrx, usb1_sbtx, usb1_usb4, usb2phy_ac,
                vsense_trigger ]

    required:
      - pins

required:
  - compatible
  - reg

unevaluatedProperties: false

examples:
  - |
    #include <dt-bindings/interrupt-controller/arm-gic.h>
    pinctrl@f100000 {
        compatible = "qcom,sc8280xp-tlmm";
        reg = <0x0f100000 0x300000>;
        interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
        gpio-controller;
        #gpio-cells = <2>;
        interrupt-controller;
        #interrupt-cells = <2>;
        gpio-ranges = <&tlmm 0 0 230>;

        gpio-wo-subnode-state {
            pins = "gpio1";
            function = "gpio";
        };

        uart-w-subnodes-state {
            rx-pins {
                pins = "gpio4";
                function = "qup14";
                bias-pull-up;
            };

            tx-pins {
                pins = "gpio5";
                function = "qup14";
                bias-disable;
            };
        };
    };
...