1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2%YAML 1.2 3--- 4$id: http://devicetree.org/schemas/pinctrl/qcom,qcs404-pinctrl.yaml# 5$schema: http://devicetree.org/meta-schemas/core.yaml# 6 7title: Qualcomm QCS404 TLMM pin controller 8 9maintainers: 10 - Bjorn Andersson <andersson@kernel.org> 11 - Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> 12 13description: 14 Top Level Mode Multiplexer pin controller in Qualcomm QCS404 SoC. 15 16properties: 17 compatible: 18 const: qcom,qcs404-pinctrl 19 20 reg: 21 maxItems: 3 22 23 reg-names: 24 items: 25 - const: south 26 - const: north 27 - const: east 28 29 interrupts: true 30 interrupt-controller: true 31 "#interrupt-cells": true 32 gpio-controller: true 33 "#gpio-cells": true 34 gpio-ranges: true 35 wakeup-parent: true 36 37 gpio-reserved-ranges: 38 minItems: 1 39 maxItems: 60 40 41 gpio-line-names: 42 maxItems: 120 43 44patternProperties: 45 "-state$": 46 oneOf: 47 - $ref: "#/$defs/qcom-qcs404-tlmm-state" 48 - patternProperties: 49 "-pins$": 50 $ref: "#/$defs/qcom-qcs404-tlmm-state" 51 additionalProperties: false 52 53$defs: 54 qcom-qcs404-tlmm-state: 55 type: object 56 description: 57 Pinctrl node's client devices use subnodes for desired pin configuration. 58 Client device subnodes use below standard properties. 59 $ref: qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state 60 61 properties: 62 pins: 63 description: 64 List of gpio pins affected by the properties specified in this 65 subnode. 66 items: 67 oneOf: 68 - pattern: "^gpio([0-9]|[1-9][0-9]|1[0-1][0-9])$" 69 - enum: [ sdc1_clk, sdc1_cmd, sdc1_data, sdc1_rclk, sdc2_clk, 70 sdc2_cmd, sdc2_data, ufs_reset ] 71 minItems: 1 72 maxItems: 36 73 74 function: 75 description: 76 Specify the alternative function to be configured for the specified 77 pins. 78 79 enum: [ gpio, adsp_ext, atest_char, atest_char0, atest_char1, 80 atest_char2, atest_char3, aud_cdc, audio_ts, bimc_dte0, 81 bimc_dte1, blsp_i2c0, blsp_i2c1, blsp_i2c3, blsp_i2c4, 82 blsp_i2c5, blsp_i2c_scl_a2, blsp_i2c_scl_b2, blsp_i2c_sda_a2, 83 blsp_i2c_sda_b2, blsp_spi0, blsp_spi2, blsp_spi3, blsp_spi4, 84 blsp_spi5, blsp_spi_clk_a1, blsp_spi_clk_b1, blsp_spi_cs_n_a1, 85 blsp_spi_cs_n_b1, blsp_spi_miso_a1, blsp_spi_miso_b1, 86 blsp_spi_mosi_a1, blsp_spi_mosi_b1, blsp_uart0, blsp_uart1, 87 blsp_uart2, blsp_uart3, blsp_uart5, blsp_uart_rx_a2, 88 blsp_uart_rx_b2, blsp_uart_tx_a2, blsp_uart_tx_b2, cri_trng, 89 cri_trng0, cri_trng1, dbg_out, dsd_clk_a, dsd_clk_b, ebi2_a, 90 ebi2_lcd, ebi_cdc, ebi_ch0, ext_lpass, ext_mclk0, ext_mclk1_a, 91 ext_mclk1_b, gcc_gp1_clk_a, gcc_gp1_clk_b, gcc_gp2_clk_a, 92 gcc_gp2_clk_b, gcc_gp3_clk_a, gcc_gp3_clk_b, gcc_plltest, 93 gcc_tlmm, hdmi_ddc, hdmi_dtest, hdmi_lbk0, hdmi_lbk1, 94 hdmi_lbk2, hdmi_lbk3, hdmi_lbk4, hdmi_lbk5, hdmi_lbk6, 95 hdmi_lbk7, hdmi_lbk8, hdmi_lbk9, hdmi_pixel, hdmi_rcv, hdmi_tx, 96 i2s_1, i2s_2, i2s_3_data0_a, i2s_3_data0_b, i2s_3_data1_a, 97 i2s_3_data1_b, i2s_3_data2_a, i2s_3_data2_b, i2s_3_data3_a, 98 i2s_3_data3_b, i2s_3_sck_a, i2s_3_sck_b, i2s_3_ws_a, 99 i2s_3_ws_b, i2s_4, ir_in, ldo_en, ldo_update, mclk_in1, 100 mclk_in2, m_voc, nfc_dwl, nfc_irq, pcie_clk, pll_bist, 101 prng_rosc, pwm_led1, pwm_led10, pwm_led11, pwm_led12, 102 pwm_led13, pwm_led14, pwm_led15, pwm_led16, pwm_led17, 103 pwm_led18, pwm_led19, pwm_led2, pwm_led20, pwm_led21, 104 pwm_led22, pwm_led23, pwm_led24, pwm_led3, pwm_led4, pwm_led5, 105 pwm_led6, pwm_led7, pwm_led8, pwm_led9, qdss_cti_trig_in_a0, 106 qdss_cti_trig_in_a1, qdss_cti_trig_in_b0, qdss_cti_trig_in_b1, 107 qdss_cti_trig_out_a0, qdss_cti_trig_out_a1, 108 qdss_cti_trig_out_b0, qdss_cti_trig_out_b1, qdss_traceclk_a, 109 qdss_traceclk_b, qdss_tracectl_a, qdss_tracectl_b, 110 qdss_tracedata_a, qdss_tracedata_b, rgb_clk, rgb_data0, 111 rgb_data1, rgb_data2, rgb_data3, rgb_data4, rgb_data5, 112 rgb_data6, rgb_data7, rgb_data_b0, rgb_data_b1, rgb_data_b2, 113 rgb_data_b3, rgb_data_b4, rgb_data_b5, rgb_data_b6, 114 rgb_data_b7, rgb_de, rgb_hsync, rgb_mdp, rgb_vsync, rgmi_dll1, 115 rgmi_dll2, rgmii_ck, rgmii_ctl, rgmii_int, rgmii_mdc, 116 rgmii_mdio, rgmii_rx, rgmii_tx, rgmii_wol, sd_write, 117 spdifrx_opt, spi_lcd, spkr_dac0, wlan1_adc0, wlan1_adc1, 118 wlan2_adc0, wlan2_adc1, wsa_en ] 119 120 bias-pull-down: true 121 bias-pull-up: true 122 bias-disable: true 123 drive-strength: true 124 input-enable: true 125 output-high: true 126 output-low: true 127 128 required: 129 - pins 130 131 additionalProperties: false 132 133allOf: 134 - $ref: /schemas/pinctrl/qcom,tlmm-common.yaml# 135 136required: 137 - compatible 138 - reg 139 140additionalProperties: false 141 142examples: 143 - | 144 #include <dt-bindings/interrupt-controller/arm-gic.h> 145 146 tlmm: pinctrl@1000000 { 147 compatible = "qcom,qcs404-pinctrl"; 148 reg = <0x01000000 0x200000>, 149 <0x01300000 0x200000>, 150 <0x07b00000 0x200000>; 151 reg-names = "south", "north", "east"; 152 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; 153 gpio-ranges = <&tlmm 0 0 120>; 154 gpio-controller; 155 #gpio-cells = <2>; 156 interrupt-controller; 157 #interrupt-cells = <2>; 158 159 160 blsp1-i2c1-default-state { 161 pins = "gpio24", "gpio25"; 162 function = "blsp_i2c1"; 163 }; 164 165 blsp1-i2c2-default-state { 166 sda-pins { 167 pins = "gpio19"; 168 function = "blsp_i2c_sda_a2"; 169 }; 170 171 scl-pins { 172 pins = "gpio20"; 173 function = "blsp_i2c_scl_a2"; 174 }; 175 }; 176 }; 177