xref: /linux/Documentation/devicetree/bindings/pinctrl/qcom,msm8953-pinctrl.yaml (revision 03c11eb3b16dc0058589751dfd91f254be2be613) 
1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/pinctrl/qcom,msm8953-pinctrl.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Qualcomm Technologies, Inc. MSM8953 TLMM block
8
9maintainers:
10  - Bjorn Andersson <bjorn.andersson@linaro.org>
11
12description:
13  Top Level Mode Multiplexer pin controller in Qualcomm MSM8953 SoC.
14
15properties:
16  compatible:
17    const: qcom,msm8953-pinctrl
18
19  reg:
20    maxItems: 1
21
22  interrupts:
23    maxItems: 1
24
25  gpio-reserved-ranges: true
26
27patternProperties:
28  "-state$":
29    oneOf:
30      - $ref: "#/$defs/qcom-msm8953-tlmm-state"
31      - patternProperties:
32          "-pins$":
33            $ref: "#/$defs/qcom-msm8953-tlmm-state"
34        additionalProperties: false
35
36$defs:
37  qcom-msm8953-tlmm-state:
38    type: object
39    description:
40      Pinctrl node's client devices use subnodes for desired pin configuration.
41      Client device subnodes use below standard properties.
42    $ref: qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state
43    unevaluatedProperties: false
44
45    properties:
46      pins:
47        description:
48          List of gpio pins affected by the properties specified in this
49          subnode.
50        items:
51          oneOf:
52            - pattern: "^gpio([0-9]|[1-9][0-9]|1[0-3][0-9]|14[01])$"
53            - enum: [ sdc1_clk, sdc1_cmd, sdc1_data, sdc1_rclk, sdc2_clk,
54                      sdc2_cmd, sdc2_data, qdsd_clk, qdsd_cmd, qdsd_data0,
55                      qdsd_data1, qdsd_data2, qdsd_data3 ]
56        minItems: 1
57        maxItems: 16
58
59      function:
60        description:
61          Specify the alternative function to be configured for the specified
62          pins.
63
64        enum: [ accel_int, adsp_ext, alsp_int, atest_bbrx0, atest_bbrx1,
65                atest_char, atest_char0, atest_char1, atest_char2, atest_char3,
66                atest_gpsadc_dtest0_native, atest_gpsadc_dtest1_native, atest_tsens,
67                atest_wlan0, atest_wlan1, bimc_dte0, bimc_dte1, blsp1_spi,
68                blsp3_spi, blsp6_spi, blsp7_spi, blsp_i2c1, blsp_i2c2, blsp_i2c3,
69                blsp_i2c4, blsp_i2c5, blsp_i2c6, blsp_i2c7, blsp_i2c8, blsp_spi1,
70                blsp_spi2, blsp_spi3, blsp_spi4, blsp_spi5, blsp_spi6, blsp_spi7,
71                blsp_spi8, blsp_uart2, blsp_uart4, blsp_uart5, blsp_uart6, cam0_ldo,
72                cam1_ldo, cam1_rst, cam1_standby, cam2_rst, cam2_standby, cam3_rst,
73                cam3_standby, cam_irq, cam_mclk, cap_int, cci_async, cci_i2c,
74                cci_timer0, cci_timer1, cci_timer2, cci_timer3, cci_timer4,
75                cdc_pdm0, codec_int1, codec_int2, codec_reset, cri_trng, cri_trng0,
76                cri_trng1, dac_calib0, dac_calib1, dac_calib10, dac_calib11,
77                dac_calib12, dac_calib13, dac_calib14, dac_calib15, dac_calib16,
78                dac_calib17, dac_calib18, dac_calib19, dac_calib2, dac_calib20,
79                dac_calib21, dac_calib22, dac_calib23, dac_calib24, dac_calib25,
80                dac_calib3, dac_calib4, dac_calib5, dac_calib6, dac_calib7,
81                dac_calib8, dac_calib9, dbg_out, ddr_bist, dmic0_clk, dmic0_data,
82                ebi_cdc, ebi_ch0, ext_lpass, flash_strobe, fp_int, gcc_gp1_clk_a,
83                gcc_gp1_clk_b, gcc_gp2_clk_a, gcc_gp2_clk_b, gcc_gp3_clk_a,
84                gcc_gp3_clk_b, gcc_plltest, gcc_tlmm, gpio, gsm0_tx, gsm1_tx,
85                gyro_int, hall_int, hdmi_int, key_focus, key_home, key_snapshot,
86                key_volp, ldo_en, ldo_update, lpass_slimbus, lpass_slimbus0,
87                lpass_slimbus1, m_voc, mag_int, mdp_vsync, mipi_dsi0, modem_tsync,
88                mss_lte, nav_pps, nav_pps_in_a, nav_pps_in_b, nav_tsync,
89                nfc_disable, nfc_dwl, nfc_irq, ois_sync, pa_indicator, pbs0, pbs1,
90                pbs2, pressure_int, pri_mi2s, pri_mi2s_mclk_a, pri_mi2s_mclk_b,
91                pri_mi2s_ws, prng_rosc, pwr_crypto_enabled_a, pwr_crypto_enabled_b,
92                pwr_down, pwr_modem_enabled_a, pwr_modem_enabled_b,
93                pwr_nav_enabled_a, pwr_nav_enabled_b, qdss_cti_trig_in_a0,
94                qdss_cti_trig_in_a1, qdss_cti_trig_in_b0, qdss_cti_trig_in_b1,
95                qdss_cti_trig_out_a0, qdss_cti_trig_out_a1, qdss_cti_trig_out_b0,
96                qdss_cti_trig_out_b1, qdss_traceclk_a, qdss_traceclk_b,
97                qdss_tracectl_a, qdss_tracectl_b, qdss_tracedata_a,
98                qdss_tracedata_b, sd_write, sdcard_det, sec_mi2s, sec_mi2s_mclk_a,
99                sec_mi2s_mclk_b, smb_int, ss_switch, ssbi_wtr1, ts_resout,
100                ts_sample, ts_xvdd, tsens_max, uim1_clk, uim1_data, uim1_present,
101                uim1_reset, uim2_clk, uim2_data, uim2_present, uim2_reset,
102                uim_batt, us_emitter, us_euro, wcss_bt, wcss_fm, wcss_wlan,
103                wcss_wlan0, wcss_wlan1, wcss_wlan2, wsa_en, wsa_io, wsa_irq ]
104
105    required:
106      - pins
107
108allOf:
109  - $ref: /schemas/pinctrl/qcom,tlmm-common.yaml#
110
111required:
112  - compatible
113  - reg
114
115unevaluatedProperties: false
116
117examples:
118  - |
119    #include <dt-bindings/interrupt-controller/arm-gic.h>
120    tlmm: pinctrl@1000000 {
121        compatible = "qcom,msm8953-pinctrl";
122        reg = <0x01000000 0x300000>;
123        interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
124        interrupt-controller;
125        #interrupt-cells = <2>;
126        gpio-controller;
127        #gpio-cells = <2>;
128        gpio-ranges = <&tlmm 0 0 142>;
129
130        serial_default: serial-state {
131            pins = "gpio4", "gpio5";
132            function = "blsp_uart2";
133            drive-strength = <2>;
134            bias-disable;
135        };
136    };
137