1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2%YAML 1.2 3--- 4$id: http://devicetree.org/schemas/pinctrl/pinctrl-single.yaml# 5$schema: http://devicetree.org/meta-schemas/core.yaml# 6 7title: Generic Pin Controller with a Single Register for One or More Pins 8 9maintainers: 10 - Tony Lindgren <tony@atomide.com> 11 12description: 13 Some pin controller devices use a single register for one or more pins. The 14 range of pin control registers can vary from one to many for each controller 15 instance. Some SoCs from Altera, Broadcom, HiSilicon, Ralink, and TI have this 16 kind of pin controller instances. 17 18properties: 19 compatible: 20 oneOf: 21 - enum: 22 - pinctrl-single 23 - pinconf-single 24 - items: 25 - enum: 26 - ti,am437-padconf 27 - ti,am654-padconf 28 - ti,dra7-padconf 29 - ti,omap2420-padconf 30 - ti,omap2430-padconf 31 - ti,omap3-padconf 32 - ti,omap4-padconf 33 - ti,omap5-padconf 34 - ti,j7200-padconf 35 - const: pinctrl-single 36 37 reg: 38 maxItems: 1 39 40 interrupt-controller: true 41 42 '#interrupt-cells': 43 const: 1 44 45 '#address-cells': 46 const: 1 47 48 '#size-cells': 49 const: 0 50 51 '#pinctrl-cells': 52 description: 53 Number of cells. Usually 2, consisting of register offset, pin configuration 54 value, and pinmux mode. Some controllers may use 1 for just offset and value. 55 enum: [ 1, 2 ] 56 57 pinctrl-single,bit-per-mux: 58 description: Optional flag to indicate register controls more than one pin 59 type: boolean 60 61 pinctrl-single,function-mask: 62 description: Mask of the allowed register bits 63 $ref: /schemas/types.yaml#/definitions/uint32 64 65 pinctrl-single,function-off: 66 description: Optional function off mode for disabled state 67 $ref: /schemas/types.yaml#/definitions/uint32 68 69 pinctrl-single,register-width: 70 description: Width of pin specific bits in the register 71 $ref: /schemas/types.yaml#/definitions/uint32 72 enum: [ 8, 16, 32 ] 73 74 pinctrl-single,gpio-range: 75 description: Optional list of pin base, nr pins & gpio function 76 $ref: /schemas/types.yaml#/definitions/phandle-array 77 items: 78 - items: 79 - description: phandle of a gpio-range node 80 - description: pin base 81 - description: number of pins 82 - description: gpio function 83 84 '#gpio-range-cells': 85 description: No longer needed, may exist in older files for gpio-ranges 86 deprecated: true 87 const: 3 88 89 gpio-range: 90 description: Optional node for gpio range cells 91 type: object 92 additionalProperties: false 93 properties: 94 '#pinctrl-single,gpio-range-cells': 95 description: Number of gpio range cells 96 const: 3 97 $ref: /schemas/types.yaml#/definitions/uint32 98 99patternProperties: 100 '-pins(-[0-9]+)?$|-pin$': 101 description: 102 Pin group node name using naming ending in -pins followed by an optional 103 instance number 104 type: object 105 additionalProperties: false 106 107 properties: 108 pinctrl-single,pins: 109 description: 110 Array of pins as described in pinmux-node.yaml for pinctrl-pin-array 111 $ref: /schemas/types.yaml#/definitions/uint32-array 112 113 pinctrl-single,bits: 114 description: Register bit configuration for pinctrl-single,bit-per-mux 115 $ref: /schemas/types.yaml#/definitions/uint32-array 116 items: 117 - description: register offset 118 - description: value 119 - description: pin bitmask in the register 120 121 pinctrl-single,bias-pullup: 122 description: Optional bias pull up configuration 123 $ref: /schemas/types.yaml#/definitions/uint32-array 124 items: 125 - description: input 126 - description: enabled pull up bits 127 - description: disabled pull up bits 128 - description: bias pull up mask 129 130 pinctrl-single,bias-pulldown: 131 description: Optional bias pull down configuration 132 $ref: /schemas/types.yaml#/definitions/uint32-array 133 items: 134 - description: input 135 - description: enabled pull down bits 136 - description: disabled pull down bits 137 - description: bias pull down mask 138 139 pinctrl-single,drive-strength: 140 description: Optional drive strength configuration 141 $ref: /schemas/types.yaml#/definitions/uint32-array 142 items: 143 - description: drive strength current 144 - description: drive strength mask 145 146 pinctrl-single,input-schmitt: 147 description: Optional input schmitt configuration 148 $ref: /schemas/types.yaml#/definitions/uint32-array 149 items: 150 - description: input 151 - description: enable bits 152 - description: disable bits 153 - description: input schmitt mask 154 155 pinctrl-single,low-power-mode: 156 description: Optional low power mode configuration 157 $ref: /schemas/types.yaml#/definitions/uint32-array 158 items: 159 - description: low power mode value 160 - description: low power mode mask 161 162 pinctrl-single,slew-rate: 163 description: Optional slew rate configuration 164 $ref: /schemas/types.yaml#/definitions/uint32-array 165 items: 166 - description: slew rate 167 - description: slew rate mask 168 169allOf: 170 - $ref: pinctrl.yaml# 171 172required: 173 - compatible 174 - reg 175 - pinctrl-single,register-width 176 177additionalProperties: false 178 179examples: 180 - | 181 soc { 182 #address-cells = <1>; 183 #size-cells = <1>; 184 185 pinmux@4a100040 { 186 compatible = "pinctrl-single"; 187 reg = <0x4a100040 0x0196>; 188 #address-cells = <1>; 189 #size-cells = <0>; 190 #pinctrl-cells = <2>; 191 #interrupt-cells = <1>; 192 interrupt-controller; 193 pinctrl-single,register-width = <16>; 194 pinctrl-single,function-mask = <0xffff>; 195 pinctrl-single,gpio-range = <&range 0 3 0>; 196 range: gpio-range { 197 #pinctrl-single,gpio-range-cells = <3>; 198 }; 199 200 uart2-pins { 201 pinctrl-single,pins = 202 <0xd8 0x118>, 203 <0xda 0>, 204 <0xdc 0x118>, 205 <0xde 0>; 206 }; 207 }; 208 }; 209