xref: /linux/Documentation/devicetree/bindings/pinctrl/pinctrl-single.yaml (revision 5ea5880764cbb164afb17a62e76ca75dc371409d) 
1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/pinctrl/pinctrl-single.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Generic Pin Controller with a Single Register for One or More Pins
8
9maintainers:
10  - Tony Lindgren <tony@atomide.com>
11
12description:
13  Some pin controller devices use a single register for one or more pins. The
14  range of pin control registers can vary from one to many for each controller
15  instance. Some SoCs from Altera, Broadcom, HiSilicon, Ralink, and TI have this
16  kind of pin controller instances.
17
18properties:
19  compatible:
20    oneOf:
21      - enum:
22          - pinctrl-single
23          - pinconf-single
24      - items:
25          - enum:
26              - ti,am437-padconf
27              - ti,am62l-padconf
28              - ti,am654-padconf
29              - ti,dra7-padconf
30              - ti,omap2420-padconf
31              - ti,omap2430-padconf
32              - ti,omap3-padconf
33              - ti,omap4-padconf
34              - ti,omap5-padconf
35              - ti,j7200-padconf
36          - const: pinctrl-single
37      - items:
38          - enum:
39              - marvell,pxa1908-padconf
40          - const: pinconf-single
41      - items:
42          - enum:
43              - brcm,bcm7038-padconf
44          - const: pinctrl-single
45
46  reg:
47    maxItems: 1
48
49  interrupt-controller: true
50
51  '#interrupt-cells':
52    const: 1
53
54  '#address-cells':
55    const: 1
56
57  '#size-cells':
58    const: 0
59
60  '#pinctrl-cells':
61    description:
62      Number of cells. Usually 2, consisting of register offset, pin configuration
63      value, and pinmux mode. Some controllers may use 1 for just offset and value.
64    enum: [ 1, 2 ]
65
66  pinctrl-single,bit-per-mux:
67    description: Optional flag to indicate register controls more than one pin
68    type: boolean
69
70  pinctrl-single,function-mask:
71    description: Mask of the allowed register bits
72    $ref: /schemas/types.yaml#/definitions/uint32
73
74  pinctrl-single,function-off:
75    description: Optional function off mode for disabled state
76    $ref: /schemas/types.yaml#/definitions/uint32
77
78  pinctrl-single,register-width:
79    description: Width of pin specific bits in the register
80    $ref: /schemas/types.yaml#/definitions/uint32
81    enum: [ 8, 16, 32 ]
82
83  pinctrl-single,gpio-range:
84    description: Optional list of pin base, nr pins & gpio function
85    $ref: /schemas/types.yaml#/definitions/phandle-array
86    items:
87      items:
88        - description: phandle of a gpio-range node
89        - description: pin base
90        - description: number of pins
91        - description: gpio function
92
93  '#gpio-range-cells':
94    description: No longer needed, may exist in older files for gpio-ranges
95    deprecated: true
96    const: 3
97
98  gpio-range:
99    description: Optional node for gpio range cells
100    type: object
101    additionalProperties: false
102    properties:
103      '#pinctrl-single,gpio-range-cells':
104        description: Number of gpio range cells
105        const: 3
106        $ref: /schemas/types.yaml#/definitions/uint32
107
108patternProperties:
109  '-pins(-[0-9]+)?$|-pin$':
110    description:
111      Pin group node name using naming ending in -pins followed by an optional
112      instance number
113    type: object
114    additionalProperties: false
115
116    properties:
117      pinctrl-single,pins:
118        description:
119          Array of pins as described in pinmux-node.yaml for pinctrl-pin-array
120        $ref: /schemas/types.yaml#/definitions/uint32-array
121
122      pinctrl-single,bits:
123        description: Register bit configuration for pinctrl-single,bit-per-mux
124        $ref: /schemas/types.yaml#/definitions/uint32-array
125        items:
126          - description: register offset
127          - description: value
128          - description: pin bitmask in the register
129
130      pinctrl-single,bias-pullup:
131        description: Optional bias pull up configuration
132        $ref: /schemas/types.yaml#/definitions/uint32-array
133        items:
134          - description: input
135          - description: enabled pull up bits
136          - description: disabled pull up bits
137          - description: bias pull up mask
138
139      pinctrl-single,bias-pulldown:
140        description: Optional bias pull down configuration
141        $ref: /schemas/types.yaml#/definitions/uint32-array
142        items:
143          - description: input
144          - description: enabled pull down bits
145          - description: disabled pull down bits
146          - description: bias pull down mask
147
148      pinctrl-single,drive-strength:
149        description: Optional drive strength configuration
150        $ref: /schemas/types.yaml#/definitions/uint32-array
151        items:
152          - description: drive strength current
153          - description: drive strength mask
154
155      pinctrl-single,input-schmitt:
156        description: Optional schmitt strength configuration
157        $ref: /schemas/types.yaml#/definitions/uint32-array
158        items:
159          - description: schmitt strength current
160          - description: schmitt strength mask
161
162      pinctrl-single,input-schmitt-enable:
163        description: Optional input schmitt configuration
164        $ref: /schemas/types.yaml#/definitions/uint32-array
165        items:
166          - description: input
167          - description: enable bits
168          - description: disable bits
169          - description: input schmitt mask
170
171      pinctrl-single,low-power-mode:
172        description: Optional low power mode configuration
173        $ref: /schemas/types.yaml#/definitions/uint32-array
174        items:
175          - description: low power mode value
176          - description: low power mode mask
177
178      pinctrl-single,slew-rate:
179        description: Optional slew rate configuration
180        $ref: /schemas/types.yaml#/definitions/uint32-array
181        items:
182          - description: slew rate
183          - description: slew rate mask
184
185allOf:
186  - $ref: pinctrl.yaml#
187
188required:
189  - compatible
190  - reg
191  - pinctrl-single,register-width
192
193additionalProperties: false
194
195examples:
196  - |
197    soc {
198      #address-cells = <1>;
199      #size-cells = <1>;
200
201      pinmux@4a100040 {
202        compatible = "pinctrl-single";
203        reg = <0x4a100040 0x0196>;
204        #address-cells = <1>;
205        #size-cells = <0>;
206        #pinctrl-cells = <2>;
207        #interrupt-cells = <1>;
208        interrupt-controller;
209        pinctrl-single,register-width = <16>;
210        pinctrl-single,function-mask = <0xffff>;
211        pinctrl-single,gpio-range = <&range 0 3 0>;
212        range: gpio-range {
213          #pinctrl-single,gpio-range-cells = <3>;
214        };
215
216        uart2-pins {
217          pinctrl-single,pins =
218            <0xd8 0x118>,
219            <0xda 0>,
220            <0xdc 0x118>,
221            <0xde 0>;
222        };
223      };
224    };
225