1*30a9d516SPrathamesh Shete# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2*30a9d516SPrathamesh Shete%YAML 1.2 3*30a9d516SPrathamesh Shete--- 4*30a9d516SPrathamesh Shete$id: http://devicetree.org/schemas/pinctrl/nvidia,tegra264-pinmux-main.yaml# 5*30a9d516SPrathamesh Shete$schema: http://devicetree.org/meta-schemas/core.yaml# 6*30a9d516SPrathamesh Shete 7*30a9d516SPrathamesh Shetetitle: NVIDIA Tegra264 Main Pinmux Controller 8*30a9d516SPrathamesh Shete 9*30a9d516SPrathamesh Shetemaintainers: 10*30a9d516SPrathamesh Shete - Thierry Reding <thierry.reding@gmail.com> 11*30a9d516SPrathamesh Shete - Jon Hunter <jonathanh@nvidia.com> 12*30a9d516SPrathamesh Shete 13*30a9d516SPrathamesh Sheteproperties: 14*30a9d516SPrathamesh Shete compatible: 15*30a9d516SPrathamesh Shete const: nvidia,tegra264-pinmux-main 16*30a9d516SPrathamesh Shete 17*30a9d516SPrathamesh Shete reg: 18*30a9d516SPrathamesh Shete maxItems: 1 19*30a9d516SPrathamesh Shete 20*30a9d516SPrathamesh ShetepatternProperties: 21*30a9d516SPrathamesh Shete "^pinmux(-[a-z0-9-]+)?$": 22*30a9d516SPrathamesh Shete type: object 23*30a9d516SPrathamesh Shete 24*30a9d516SPrathamesh Shete # pin groups 25*30a9d516SPrathamesh Shete additionalProperties: 26*30a9d516SPrathamesh Shete $ref: nvidia,tegra264-pinmux-common.yaml 27*30a9d516SPrathamesh Shete 28*30a9d516SPrathamesh Shete properties: 29*30a9d516SPrathamesh Shete nvidia,pins: 30*30a9d516SPrathamesh Shete items: 31*30a9d516SPrathamesh Shete enum: [ pwm1_pa0, pwm6_pa1, pwm7_pa2, pwm8_pa3, ufs0_ref_clk_pa4, 32*30a9d516SPrathamesh Shete ufs0_rst_n_pa5, soc_gpio250_pf0, soc_gpio251_pf1, 33*30a9d516SPrathamesh Shete soc_gpio252_pf2, dp_aux_ch0_hpd_pf3, dp_aux_ch1_hpd_pf4, 34*30a9d516SPrathamesh Shete dp_aux_ch2_hpd_pf5, dp_aux_ch3_hpd_pf6, pwm2_pf7, pwm3_pg0, 35*30a9d516SPrathamesh Shete gen7_i2c_scl_pg1, gen7_i2c_sda_pg2, gen9_i2c_scl_pg3, 36*30a9d516SPrathamesh Shete gen9_i2c_sda_pg4, sdmmc1_clk_px0, sdmmc1_cmd_px1, 37*30a9d516SPrathamesh Shete sdmmc1_dat0_px2, sdmmc1_dat1_px3, sdmmc1_dat2_px4, 38*30a9d516SPrathamesh Shete sdmmc1_dat3_px5, sdmmc1_comp, soc_gpio124_pl0, 39*30a9d516SPrathamesh Shete soc_gpio125_pl1, fan_tach0_pl2, soc_gpio127_pl3, 40*30a9d516SPrathamesh Shete soc_gpio128_pl4, soc_gpio129_pl5, soc_gpio130_pl6, 41*30a9d516SPrathamesh Shete soc_gpio131_pl7, gp_pwm9_pm0, soc_gpio133_pm1, uart9_tx_pm2, 42*30a9d516SPrathamesh Shete uart9_rx_pm3, uart9_rts_n_pm4, uart9_cts_n_pm5, 43*30a9d516SPrathamesh Shete soc_gpio170_pu0, soc_gpio171_pu1, soc_gpio172_pu2, 44*30a9d516SPrathamesh Shete soc_gpio173_pu3, soc_gpio174_pu4, soc_gpio175_pu5, 45*30a9d516SPrathamesh Shete soc_gpio176_pu6, soc_gpio177_pu7, soc_gpio178_pv0, 46*30a9d516SPrathamesh Shete pwm10_pv1, uart4_tx_pv2, uart4_rx_pv3, uart4_rts_n_pv4, 47*30a9d516SPrathamesh Shete uart4_cts_n_pv5, dap2_clk_pv6, dap2_din_pv7, dap2_dout_pw0, 48*30a9d516SPrathamesh Shete dap2_fs_pw1, gen1_i2c_scl_pw2, gen1_i2c_sda_pw3, 49*30a9d516SPrathamesh Shete gen0_i2c_scl_pw4, gen0_i2c_sda_pw5, pwr_i2c_scl_pw6, 50*30a9d516SPrathamesh Shete pwr_i2c_sda_pw7, soc_gpio138_pp0, soc_gpio139_pp1, 51*30a9d516SPrathamesh Shete dap6_sclk_pp2, dap6_dout_pp3, dap6_din_pp4, dap6_fs_pp5, 52*30a9d516SPrathamesh Shete dap4_sclk_pp6, dap4_dout_pp7, dap4_din_pq0, dap4_fs_pq1, 53*30a9d516SPrathamesh Shete spi5_sck_pq2, spi5_miso_pq3, spi5_mosi_pq4, spi5_cs0_pq5, 54*30a9d516SPrathamesh Shete soc_gpio152_pq6, soc_gpio153_pq7, aud_mclk_pr0, 55*30a9d516SPrathamesh Shete soc_gpio155_pr1, dap1_sclk_pr2, dap1_out_pr3, dap1_in_pr4, 56*30a9d516SPrathamesh Shete dap1_fs_pr5, gen11_i2c_scl_pr6, gen11_i2c_sda_pr7, 57*30a9d516SPrathamesh Shete soc_gpio350_ps0, soc_gpio351_ps1, qspi0_sck_pt0, 58*30a9d516SPrathamesh Shete qspi0_cs_n_pt1, qspi0_io0_pt2, qspi0_io1_pt3, qspi0_io2_pt4, 59*30a9d516SPrathamesh Shete qspi0_io3_pt5, soc_gpio192_pt6, soc_gpio270_py0, 60*30a9d516SPrathamesh Shete soc_gpio271_py1, soc_gpio272_py2, soc_gpio273_py3, 61*30a9d516SPrathamesh Shete soc_gpio274_py4, soc_gpio275_py5, soc_gpio276_py6, 62*30a9d516SPrathamesh Shete soc_gpio277_py7, soc_gpio278_pz0, soc_gpio279_pz1, 63*30a9d516SPrathamesh Shete xhalt_trig_pz2, soc_gpio281_pz3, soc_gpio282_pz4, 64*30a9d516SPrathamesh Shete soc_gpio283_pz5, soc_gpio284_pz6, soc_gpio285_pz7, 65*30a9d516SPrathamesh Shete soc_gpio286_pal0, soc_gpio287_pal1, soc_gpio288_pal2, 66*30a9d516SPrathamesh Shete cpu_pwr_req_ph0, gpu_pwr_req_ph1, uart10_tx_ph2, 67*30a9d516SPrathamesh Shete uart10_rx_ph3, uart10_rts_n_ph4, uart10_cts_n_ph5, 68*30a9d516SPrathamesh Shete spi3_sck_ph6, spi3_miso_ph7, spi3_mosi_pj0, spi3_cs0_pj1, 69*30a9d516SPrathamesh Shete spi3_cs3_pj2, uart5_tx_pj3, uart5_rx_pj4, uart5_rts_n_pj5, 70*30a9d516SPrathamesh Shete uart5_cts_n_pj6, spi1_sck_pj7, spi1_miso_pk0, spi1_mosi_pk1, 71*30a9d516SPrathamesh Shete spi1_cs0_pk2, spi1_cs1_pk3, extperiph1_clk_pk4, 72*30a9d516SPrathamesh Shete extperiph2_clk_pk5, gen12_i2c_scl_pk6, gen12_i2c_sda_pk7, 73*30a9d516SPrathamesh Shete drive_cpu_pwr_req_ph0, drive_gpu_pwr_req_ph1, 74*30a9d516SPrathamesh Shete drive_uart10_cts_n_ph5, drive_uart10_rts_n_ph4, 75*30a9d516SPrathamesh Shete drive_uart10_rx_ph3, drive_uart10_tx_ph2, 76*30a9d516SPrathamesh Shete drive_spi3_cs0_pj1, drive_spi3_cs3_pj2, 77*30a9d516SPrathamesh Shete drive_spi3_miso_ph7, drive_spi3_mosi_pj0, 78*30a9d516SPrathamesh Shete drive_spi3_sck_ph6, drive_uart5_cts_n_pj6, 79*30a9d516SPrathamesh Shete drive_uart5_rts_n_pj5, drive_uart5_rx_pj4, 80*30a9d516SPrathamesh Shete drive_uart5_tx_pj3, drive_spi1_cs0_pk2, 81*30a9d516SPrathamesh Shete drive_spi1_cs1_pk3, drive_spi1_miso_pk0, 82*30a9d516SPrathamesh Shete drive_spi1_mosi_pk1, drive_spi1_sck_pj7, 83*30a9d516SPrathamesh Shete drive_extperiph2_clk_pk5, drive_extperiph1_clk_pk4, 84*30a9d516SPrathamesh Shete drive_gen12_i2c_scl_pk6, drive_gen12_i2c_sda_pk7, 85*30a9d516SPrathamesh Shete drive_soc_gpio124_pl0, drive_soc_gpio125_pl1, 86*30a9d516SPrathamesh Shete drive_fan_tach0_pl2, drive_soc_gpio127_pl3, 87*30a9d516SPrathamesh Shete drive_soc_gpio128_pl4, drive_soc_gpio129_pl5, 88*30a9d516SPrathamesh Shete drive_soc_gpio130_pl6, drive_soc_gpio131_pl7, 89*30a9d516SPrathamesh Shete drive_gp_pwm9_pm0, drive_soc_gpio133_pm1, 90*30a9d516SPrathamesh Shete drive_uart9_cts_n_pm5, drive_uart9_rts_n_pm4, 91*30a9d516SPrathamesh Shete drive_uart9_rx_pm3, drive_uart9_tx_pm2, 92*30a9d516SPrathamesh Shete drive_sdmmc1_clk_px0, drive_sdmmc1_cmd_px1, 93*30a9d516SPrathamesh Shete drive_sdmmc1_dat3_px5, drive_sdmmc1_dat2_px4, 94*30a9d516SPrathamesh Shete drive_sdmmc1_dat1_px3, drive_sdmmc1_dat0_px2, 95*30a9d516SPrathamesh Shete drive_qspi0_cs_n_pt1, drive_qspi0_io0_pt2, 96*30a9d516SPrathamesh Shete drive_qspi0_io1_pt3, drive_qspi0_io2_pt4, 97*30a9d516SPrathamesh Shete drive_qspi0_io3_pt5, drive_qspi0_sck_pt0, 98*30a9d516SPrathamesh Shete drive_soc_gpio192_pt6, drive_soc_gpio138_pp0, 99*30a9d516SPrathamesh Shete drive_soc_gpio139_pp1, drive_dap6_din_pp4, 100*30a9d516SPrathamesh Shete drive_dap6_dout_pp3, drive_dap6_fs_pp5, 101*30a9d516SPrathamesh Shete drive_dap6_sclk_pp2, drive_dap4_dout_pp7, 102*30a9d516SPrathamesh Shete drive_dap4_sclk_pp6, drive_dap4_din_pq0, 103*30a9d516SPrathamesh Shete drive_dap4_fs_pq1, drive_spi5_cs0_pq5, 104*30a9d516SPrathamesh Shete drive_spi5_miso_pq3, drive_spi5_mosi_pq4, 105*30a9d516SPrathamesh Shete drive_spi5_sck_pq2, drive_soc_gpio152_pq6, 106*30a9d516SPrathamesh Shete drive_soc_gpio153_pq7, drive_soc_gpio155_pr1, 107*30a9d516SPrathamesh Shete drive_aud_mclk_pr0, drive_dap1_sclk_pr2, 108*30a9d516SPrathamesh Shete drive_dap1_in_pr4, drive_dap1_out_pr3, 109*30a9d516SPrathamesh Shete drive_dap1_fs_pr5, drive_gen11_i2c_scl_pr6, 110*30a9d516SPrathamesh Shete drive_gen11_i2c_sda_pr7, drive_soc_gpio350_ps0, 111*30a9d516SPrathamesh Shete drive_soc_gpio351_ps1, drive_gen0_i2c_scl_pw4, 112*30a9d516SPrathamesh Shete drive_gen0_i2c_sda_pw5, drive_gen1_i2c_scl_pw2, 113*30a9d516SPrathamesh Shete drive_gen1_i2c_sda_pw3, drive_dap2_fs_pw1, 114*30a9d516SPrathamesh Shete drive_dap2_clk_pv6, drive_dap2_din_pv7, 115*30a9d516SPrathamesh Shete drive_dap2_dout_pw0, drive_pwm10_pv1, 116*30a9d516SPrathamesh Shete drive_soc_gpio170_pu0, drive_soc_gpio171_pu1, 117*30a9d516SPrathamesh Shete drive_soc_gpio172_pu2, drive_soc_gpio173_pu3, 118*30a9d516SPrathamesh Shete drive_soc_gpio174_pu4, drive_soc_gpio175_pu5, 119*30a9d516SPrathamesh Shete drive_soc_gpio176_pu6, drive_soc_gpio177_pu7, 120*30a9d516SPrathamesh Shete drive_soc_gpio178_pv0, drive_uart4_cts_n_pv5, 121*30a9d516SPrathamesh Shete drive_uart4_rts_n_pv4, drive_uart4_rx_pv3, 122*30a9d516SPrathamesh Shete drive_uart4_tx_pv2, drive_pwr_i2c_sda_pw7, 123*30a9d516SPrathamesh Shete drive_pwr_i2c_scl_pw6, drive_soc_gpio250_pf0, 124*30a9d516SPrathamesh Shete drive_soc_gpio251_pf1, drive_soc_gpio252_pf2, 125*30a9d516SPrathamesh Shete drive_dp_aux_ch0_hpd_pf3, drive_dp_aux_ch1_hpd_pf4, 126*30a9d516SPrathamesh Shete drive_dp_aux_ch2_hpd_pf5, drive_dp_aux_ch3_hpd_pf6, 127*30a9d516SPrathamesh Shete drive_pwm2_pf7, drive_pwm3_pg0, 128*30a9d516SPrathamesh Shete drive_gen7_i2c_scl_pg1, drive_gen7_i2c_sda_pg2, 129*30a9d516SPrathamesh Shete drive_gen9_i2c_scl_pg3, drive_gen9_i2c_sda_pg4, 130*30a9d516SPrathamesh Shete drive_soc_gpio270_py0, drive_soc_gpio271_py1, 131*30a9d516SPrathamesh Shete drive_soc_gpio272_py2, drive_soc_gpio273_py3, 132*30a9d516SPrathamesh Shete drive_soc_gpio274_py4, drive_soc_gpio275_py5, 133*30a9d516SPrathamesh Shete drive_soc_gpio276_py6, drive_soc_gpio277_py7, 134*30a9d516SPrathamesh Shete drive_soc_gpio278_pz0, drive_soc_gpio279_pz1, 135*30a9d516SPrathamesh Shete drive_soc_gpio282_pz4, drive_soc_gpio283_pz5, 136*30a9d516SPrathamesh Shete drive_soc_gpio284_pz6, drive_soc_gpio285_pz7, 137*30a9d516SPrathamesh Shete drive_soc_gpio286_pal0, drive_soc_gpio287_pal1, 138*30a9d516SPrathamesh Shete drive_soc_gpio288_pal2, drive_xhalt_trig_pz2, 139*30a9d516SPrathamesh Shete drive_soc_gpio281_pz3 ] 140*30a9d516SPrathamesh Shete 141*30a9d516SPrathamesh Sheterequired: 142*30a9d516SPrathamesh Shete - compatible 143*30a9d516SPrathamesh Shete - reg 144*30a9d516SPrathamesh Shete 145*30a9d516SPrathamesh SheteadditionalProperties: false 146*30a9d516SPrathamesh Shete 147*30a9d516SPrathamesh Sheteexamples: 148*30a9d516SPrathamesh Shete - | 149*30a9d516SPrathamesh Shete #include <dt-bindings/pinctrl/pinctrl-tegra.h> 150*30a9d516SPrathamesh Shete 151*30a9d516SPrathamesh Shete pinmux@c281000 { 152*30a9d516SPrathamesh Shete compatible = "nvidia,tegra264-pinmux-main"; 153*30a9d516SPrathamesh Shete reg = <0xc281000 0xc000>; 154*30a9d516SPrathamesh Shete 155*30a9d516SPrathamesh Shete pinctrl-names = "default"; 156*30a9d516SPrathamesh Shete pinctrl-0 = <&state_default>; 157*30a9d516SPrathamesh Shete 158*30a9d516SPrathamesh Shete state_default: pinmux-default { 159*30a9d516SPrathamesh Shete sdmmc1 { 160*30a9d516SPrathamesh Shete nvidia,pins = "sdmmc1_clk_px0"; 161*30a9d516SPrathamesh Shete nvidia,function = "sdmmc1_cd"; 162*30a9d516SPrathamesh Shete nvidia,pull = <TEGRA_PIN_PULL_NONE>; 163*30a9d516SPrathamesh Shete nvidia,tristate = <TEGRA_PIN_DISABLE>; 164*30a9d516SPrathamesh Shete nvidia,enable-input = <TEGRA_PIN_ENABLE>; 165*30a9d516SPrathamesh Shete }; 166*30a9d516SPrathamesh Shete }; 167*30a9d516SPrathamesh Shete }; 168