1*30a9d516SPrathamesh Shete# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2*30a9d516SPrathamesh Shete%YAML 1.2 3*30a9d516SPrathamesh Shete--- 4*30a9d516SPrathamesh Shete$id: http://devicetree.org/schemas/pinctrl/nvidia,tegra264-pinmux-common.yaml# 5*30a9d516SPrathamesh Shete$schema: http://devicetree.org/meta-schemas/core.yaml# 6*30a9d516SPrathamesh Shete 7*30a9d516SPrathamesh Shetetitle: NVIDIA Tegra264 Pinmux Common Properties 8*30a9d516SPrathamesh Shete 9*30a9d516SPrathamesh Shetemaintainers: 10*30a9d516SPrathamesh Shete - Thierry Reding <thierry.reding@gmail.com> 11*30a9d516SPrathamesh Shete - Jon Hunter <jonathanh@nvidia.com> 12*30a9d516SPrathamesh Shete 13*30a9d516SPrathamesh Shete$ref: nvidia,tegra-pinmux-common.yaml 14*30a9d516SPrathamesh Shete 15*30a9d516SPrathamesh Sheteproperties: 16*30a9d516SPrathamesh Shete nvidia,function: 17*30a9d516SPrathamesh Shete enum: [ dca_vsync, dca_hsync, rsvd0, dp_aux_ch0_hpd, dp_aux_ch1_hpd, 18*30a9d516SPrathamesh Shete dp_aux_ch2_hpd, dp_aux_ch3_hpd, gp_pwm2, gp_pwm3, i2c7_clk, 19*30a9d516SPrathamesh Shete i2c7_dat, i2c9_clk, i2c9_dat, uartk_cts, uartk_rts, uartk_rxd, 20*30a9d516SPrathamesh Shete uartk_txd, spi3_cs0, spi3_cs3, spi3_din, spi3_dout, spi3_sck, 21*30a9d516SPrathamesh Shete uartf_cts, uartf_rts, uartf_rxd, uartf_txd, spi1_cs0, spi1_cs1, 22*30a9d516SPrathamesh Shete spi1_din, spi1_dout, spi1_sck, extperiph2_clk, extperiph1_clk, 23*30a9d516SPrathamesh Shete i2c12_clk, i2c12_dat, nv_therm_fan_tach0, gp_pwm9, uartj_cts, 24*30a9d516SPrathamesh Shete uartj_rts, uartj_rxd, uartj_txd, i2c0_clk, i2c0_dat, i2c1_clk, 25*30a9d516SPrathamesh Shete i2c1_dat, i2s2_lrck, i2s2_sclk, i2s2_sdata_out, i2s2_sdata_in, 26*30a9d516SPrathamesh Shete gp_pwm10, uarte_cts, uarte_rts, uarte_rxd, uarte_txd, i2c5_dat, 27*30a9d516SPrathamesh Shete i2c5_clk, i2s6_sdata_in, i2s6_sdata_out, i2s6_lrck, i2s6_sclk, 28*30a9d516SPrathamesh Shete i2s4_sdata_out, i2s4_sclk, i2s4_sdata_in, i2s4_lrck, spi5_cs0, 29*30a9d516SPrathamesh Shete spi5_din, spi5_dout, spi5_sck, aud_mclk, i2s1_sclk, i2s1_sdata_in, 30*30a9d516SPrathamesh Shete i2s1_sdata_out, i2s1_lrck, i2c11_clk, i2c11_dat, xhalt_trig, 31*30a9d516SPrathamesh Shete gp_pwm1, gp_pwm6, gp_pwm7, gp_pwm8, ufs0, pe1_clkreq_l, pe1_rst_l, 32*30a9d516SPrathamesh Shete pe2_rst_l, pe2_clkreq_l, pe3_clkreq_l, pe3_rst_l, sgmii0_sma_mdio, 33*30a9d516SPrathamesh Shete sgmii0_sma_mdc, usb_vbus_en0, usb_vbus_en1, eth1_mdio, pe4_clkreq_l, 34*30a9d516SPrathamesh Shete pe4_rst_l, pe5_clkreq_l, pe5_rst_l, eth0_mdio, eth0_mdc, eth1_mdc, 35*30a9d516SPrathamesh Shete eth2_mdio, eth2_mdc, eth3_mdio, eth3_mdc, qspi0_cs_n, qspi0_io0, 36*30a9d516SPrathamesh Shete qspi0_io1, qspi0_io2, qspi0_io3, qspi0_sck, sdmmc1_clk, sdmmc1_cmd, 37*30a9d516SPrathamesh Shete sdmmc1_comp, sdmmc1_dat3, sdmmc1_dat2, sdmmc1_dat1, sdmmc1_dat0, 38*30a9d516SPrathamesh Shete qspi3_sck, qspi3_cs0, qspi3_io0, qspi3_io1, dcb_vsync, dcb_hsync, 39*30a9d516SPrathamesh Shete dsa_lspii, dce_vsync, dce_hsync, dch_vsync, dch_hsync, bl_en, 40*30a9d516SPrathamesh Shete bl_pwm_dim0, rsvd1, soc_therm_oc3, i2s5_sclk, i2s5_sdata_in, 41*30a9d516SPrathamesh Shete extperiph3_clk, extperiph4_clk, i2s5_sdata_out, i2s5_lrck, 42*30a9d516SPrathamesh Shete sdmmc1_cd, i2s7_sdata_in, spi4_sck, spi4_din, spi4_dout, spi4_cs0, 43*30a9d516SPrathamesh Shete spi4_cs1, gp_pwm5, i2c14_clk, i2c14_dat, i2s8_sclk, i2s8_sdata_out, 44*30a9d516SPrathamesh Shete i2s8_lrck, i2s8_sdata_in, i2c16_clk, i2c16_dat, i2s3_sclk, 45*30a9d516SPrathamesh Shete i2s3_sdata_out, i2s3_sdata_in, i2s3_lrck, pm_trig1, pm_trig0, 46*30a9d516SPrathamesh Shete qspi2_sck, qspi2_cs0, qspi2_io0, qspi2_io1, dcc_vsync, dcc_hsync, 47*30a9d516SPrathamesh Shete rsvd2, dcf_vsync, dcf_hsync, soundwire1_clk, soundwire1_dat0, 48*30a9d516SPrathamesh Shete soundwire1_dat1, soundwire1_dat2, dmic2_clk, dmic2_dat, 49*30a9d516SPrathamesh Shete nv_therm_fan_tach1, i2c15_clk, i2c15_dat, i2s7_lrck, 50*30a9d516SPrathamesh Shete ccla_la_trigger_mux, i2s7_sclk, i2s7_sdata_out, dmic1_dat, 51*30a9d516SPrathamesh Shete dmic1_clk, dcd_vsync, dcd_hsync, rsvd3, dcg_vsync, dcg_hsync, 52*30a9d516SPrathamesh Shete dspk1_clk, dspk1_dat, soc_therm_oc2, istctrl_ist_done_n, 53*30a9d516SPrathamesh Shete soc_therm_oc1, tsc_edge_out0c, tsc_edge_out0d, tsc_edge_out0a, 54*30a9d516SPrathamesh Shete tsc_edge_out0b, touch_clk, hdmi_cec, i2c2_clk, i2c2_dat, i2c3_clk, 55*30a9d516SPrathamesh Shete i2c3_dat, gp_pwm4, uarta_txd, uarta_rxd, spi2_sck, spi2_din, 56*30a9d516SPrathamesh Shete spi2_dout, spi2_cs0, tsc_sync1, tsc_edge_out3, tsc_edge_out0, 57*30a9d516SPrathamesh Shete tsc_edge_out1, tsc_sync0, soundwire0_clk, soundwire0_dat0, 58*30a9d516SPrathamesh Shete l0l1_rst_out_n, l2_rst_out_n, uartl_txd, uartl_rxd, i2s9_sclk, 59*30a9d516SPrathamesh Shete i2s9_sdata_out, i2s9_sdata_in, i2s9_lrck, dmic5_dat, dmic5_clk, 60*30a9d516SPrathamesh Shete tsc_edge_out2 ] 61*30a9d516SPrathamesh Shete 62*30a9d516SPrathamesh Shete # out of the common properties, only these are allowed for Tegra264 63*30a9d516SPrathamesh Shete nvidia,pins: true 64*30a9d516SPrathamesh Shete nvidia,pull: true 65*30a9d516SPrathamesh Shete nvidia,tristate: true 66*30a9d516SPrathamesh Shete nvidia,schmitt: true 67*30a9d516SPrathamesh Shete nvidia,enable-input: true 68*30a9d516SPrathamesh Shete nvidia,open-drain: true 69*30a9d516SPrathamesh Shete nvidia,lock: true 70*30a9d516SPrathamesh Shete nvidia,drive-type: true 71*30a9d516SPrathamesh Shete nvidia,io-hv: true 72*30a9d516SPrathamesh Shete 73*30a9d516SPrathamesh Sheterequired: 74*30a9d516SPrathamesh Shete - nvidia,pins 75*30a9d516SPrathamesh Shete 76*30a9d516SPrathamesh Shete# We would typically use unevaluatedProperties here but that has the 77*30a9d516SPrathamesh Shete# downside that all the properties in the common bindings become valid 78*30a9d516SPrathamesh Shete# for all chip generations. In this case, however, we want the per-SoC 79*30a9d516SPrathamesh Shete# bindings to be able to override which of the common properties are 80*30a9d516SPrathamesh Shete# allowed, since not all pinmux generations support the same sets of 81*30a9d516SPrathamesh Shete# properties. This way, the common bindings define the format of the 82*30a9d516SPrathamesh Shete# properties but the per-SoC bindings define which of them apply to a 83*30a9d516SPrathamesh Shete# given chip. 84*30a9d516SPrathamesh SheteadditionalProperties: false 85