1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2%YAML 1.2 3--- 4$id: http://devicetree.org/schemas/pinctrl/nvidia,tegra234-pinmux.yaml# 5$schema: http://devicetree.org/meta-schemas/core.yaml# 6 7title: NVIDIA Tegra234 Pinmux Controller 8 9maintainers: 10 - Thierry Reding <thierry.reding@gmail.com> 11 - Jon Hunter <jonathanh@nvidia.com> 12 13properties: 14 compatible: 15 const: nvidia,tegra234-pinmux 16 17 reg: 18 maxItems: 1 19 20patternProperties: 21 "^pinmux(-[a-z0-9-]+)?$": 22 type: object 23 24 # pin groups 25 additionalProperties: 26 $ref: nvidia,tegra234-pinmux-common.yaml 27 28 properties: 29 nvidia,pins: 30 items: 31 enum: [ dap6_sclk_pa0, dap6_dout_pa1, dap6_din_pa2, 32 dap6_fs_pa3, dap4_sclk_pa4, dap4_dout_pa5, 33 dap4_din_pa6, dap4_fs_pa7, soc_gpio08_pb0, 34 qspi0_sck_pc0, qspi0_cs_n_pc1, 35 qspi0_io0_pc2, qspi0_io1_pc3, qspi0_io2_pc4, 36 qspi0_io3_pc5, qspi1_sck_pc6, qspi1_cs_n_pc7, 37 qspi1_io0_pd0, qspi1_io1_pd1, qspi1_io2_pd2, 38 qspi1_io3_pd3, eqos_txc_pe0, eqos_td0_pe1, 39 eqos_td1_pe2, eqos_td2_pe3, eqos_td3_pe4, 40 eqos_tx_ctl_pe5, eqos_rd0_pe6, eqos_rd1_pe7, 41 eqos_rd2_pf0, eqos_rd3_pf1, eqos_rx_ctl_pf2, 42 eqos_rxc_pf3, eqos_sma_mdio_pf4, eqos_sma_mdc_pf5, 43 soc_gpio13_pg0, soc_gpio14_pg1, soc_gpio15_pg2, 44 soc_gpio16_pg3, soc_gpio17_pg4, soc_gpio18_pg5, 45 soc_gpio19_pg6, soc_gpio20_pg7, soc_gpio21_ph0, 46 soc_gpio22_ph1, soc_gpio06_ph2, uart4_tx_ph3, 47 uart4_rx_ph4, uart4_rts_ph5, uart4_cts_ph6, 48 soc_gpio41_ph7, soc_gpio42_pi0, soc_gpio43_pi1, 49 soc_gpio44_pi2, gen1_i2c_scl_pi3, gen1_i2c_sda_pi4, 50 cpu_pwr_req_pi5, soc_gpio07_pi6, 51 sdmmc1_clk_pj0, sdmmc1_cmd_pj1, sdmmc1_dat0_pj2, 52 sdmmc1_dat1_pj3, sdmmc1_dat2_pj4, sdmmc1_dat3_pj5, 53 pex_l0_clkreq_n_pk0, pex_l0_rst_n_pk1, 54 pex_l1_clkreq_n_pk2, pex_l1_rst_n_pk3, 55 pex_l2_clkreq_n_pk4, pex_l2_rst_n_pk5, 56 pex_l3_clkreq_n_pk6, pex_l3_rst_n_pk7, 57 pex_l4_clkreq_n_pl0, pex_l4_rst_n_pl1, 58 pex_wake_n_pl2, soc_gpio34_pl3, dp_aux_ch0_hpd_pm0, 59 dp_aux_ch1_hpd_pm1, dp_aux_ch2_hpd_pm2, 60 dp_aux_ch3_hpd_pm3, soc_gpio55_pm4, soc_gpio36_pm5, 61 soc_gpio53_pm6, soc_gpio38_pm7, dp_aux_ch3_n_pn0, 62 soc_gpio39_pn1, soc_gpio40_pn2, dp_aux_ch1_p_pn3, 63 dp_aux_ch1_n_pn4, dp_aux_ch2_p_pn5, dp_aux_ch2_n_pn6, 64 dp_aux_ch3_p_pn7, extperiph1_clk_pp0, 65 extperiph2_clk_pp1, cam_i2c_scl_pp2, cam_i2c_sda_pp3, 66 soc_gpio23_pp4, soc_gpio24_pp5, soc_gpio25_pp6, 67 pwr_i2c_scl_pp7, pwr_i2c_sda_pq0, soc_gpio28_pq1, 68 soc_gpio29_pq2, soc_gpio30_pq3, soc_gpio31_pq4, 69 soc_gpio32_pq5, soc_gpio33_pq6, soc_gpio35_pq7, 70 soc_gpio37_pr0, soc_gpio56_pr1, uart1_tx_pr2, 71 uart1_rx_pr3, uart1_rts_pr4, uart1_cts_pr5, 72 soc_gpio61_pw0, soc_gpio62_pw1, gpu_pwr_req_px0, 73 cv_pwr_req_px1, gp_pwm2_px2, gp_pwm3_px3, uart2_tx_px4, 74 uart2_rx_px5, uart2_rts_px6, uart2_cts_px7, spi3_sck_py0, 75 spi3_miso_py1, spi3_mosi_py2, spi3_cs0_py3, 76 spi3_cs1_py4, uart5_tx_py5, uart5_rx_py6, 77 uart5_rts_py7, uart5_cts_pz0, usb_vbus_en0_pz1, 78 usb_vbus_en1_pz2, spi1_sck_pz3, spi1_miso_pz4, 79 spi1_mosi_pz5, spi1_cs0_pz6, spi1_cs1_pz7, 80 spi5_sck_pac0, spi5_miso_pac1, spi5_mosi_pac2, 81 spi5_cs0_pac3, soc_gpio57_pac4, soc_gpio58_pac5, 82 soc_gpio59_pac6, soc_gpio60_pac7, soc_gpio45_pad0, 83 soc_gpio46_pad1, soc_gpio47_pad2, soc_gpio48_pad3, 84 ufs0_ref_clk_pae0, ufs0_rst_n_pae1, 85 pex_l5_clkreq_n_paf0, pex_l5_rst_n_paf1, 86 pex_l6_clkreq_n_paf2, pex_l6_rst_n_paf3, 87 pex_l7_clkreq_n_pag0, pex_l7_rst_n_pag1, 88 pex_l8_clkreq_n_pag2, pex_l8_rst_n_pag3, 89 pex_l9_clkreq_n_pag4, pex_l9_rst_n_pag5, 90 pex_l10_clkreq_n_pag6, pex_l10_rst_n_pag7, 91 sdmmc1_comp, eqos_comp, qspi_comp, 92 # drive groups 93 drive_soc_gpio08_pb0, drive_soc_gpio36_pm5, 94 drive_soc_gpio53_pm6, drive_soc_gpio55_pm4, 95 drive_soc_gpio38_pm7, drive_soc_gpio39_pn1, 96 drive_soc_gpio40_pn2, drive_dp_aux_ch0_hpd_pm0, 97 drive_dp_aux_ch1_hpd_pm1, drive_dp_aux_ch2_hpd_pm2, 98 drive_dp_aux_ch3_hpd_pm3, drive_dp_aux_ch1_p_pn3, 99 drive_dp_aux_ch1_n_pn4, drive_dp_aux_ch2_p_pn5, 100 drive_dp_aux_ch2_n_pn6, drive_dp_aux_ch3_p_pn7, 101 drive_dp_aux_ch3_n_pn0, drive_pex_l2_clkreq_n_pk4, 102 drive_pex_wake_n_pl2, drive_pex_l1_clkreq_n_pk2, 103 drive_pex_l1_rst_n_pk3, drive_pex_l0_clkreq_n_pk0, 104 drive_pex_l0_rst_n_pk1, drive_pex_l2_rst_n_pk5, 105 drive_pex_l3_clkreq_n_pk6, drive_pex_l3_rst_n_pk7, 106 drive_pex_l4_clkreq_n_pl0, drive_pex_l4_rst_n_pl1, 107 drive_soc_gpio34_pl3, drive_pex_l5_clkreq_n_paf0, 108 drive_pex_l5_rst_n_paf1, drive_pex_l6_clkreq_n_paf2, 109 drive_pex_l6_rst_n_paf3, drive_pex_l10_clkreq_n_pag6, 110 drive_pex_l10_rst_n_pag7, drive_pex_l7_clkreq_n_pag0, 111 drive_pex_l7_rst_n_pag1, drive_pex_l8_clkreq_n_pag2, 112 drive_pex_l8_rst_n_pag3, drive_pex_l9_clkreq_n_pag4, 113 drive_pex_l9_rst_n_pag5, drive_sdmmc1_clk_pj0, 114 drive_sdmmc1_cmd_pj1, drive_sdmmc1_dat3_pj5, 115 drive_sdmmc1_dat2_pj4, drive_sdmmc1_dat1_pj3, 116 drive_sdmmc1_dat0_pj2 ] 117 118unevaluatedProperties: false 119 120examples: 121 - | 122 #include <dt-bindings/pinctrl/pinctrl-tegra.h> 123 124 pinmux@2430000 { 125 compatible = "nvidia,tegra234-pinmux"; 126 reg = <0x2430000 0x17000>; 127 128 pinctrl-names = "pex_rst"; 129 pinctrl-0 = <&pex_rst_c5_out_state>; 130 131 pex_rst_c5_out_state: pinmux-pex-rst-c5-out { 132 pexrst { 133 nvidia,pins = "pex_l5_rst_n_paf1"; 134 nvidia,schmitt = <TEGRA_PIN_DISABLE>; 135 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 136 nvidia,io-hv = <TEGRA_PIN_ENABLE>; 137 nvidia,tristate = <TEGRA_PIN_DISABLE>; 138 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 139 }; 140 }; 141 }; 142... 143