1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2%YAML 1.2 3--- 4$id: http://devicetree.org/schemas/pinctrl/nvidia,tegra186-pinmux.yaml# 5$schema: http://devicetree.org/meta-schemas/core.yaml# 6 7title: NVIDIA Tegra186 Pinmux Controller 8 9maintainers: 10 - Thierry Reding <thierry.reding@gmail.com> 11 - Jon Hunter <jonathanh@nvidia.com> 12 13properties: 14 compatible: 15 enum: 16 - nvidia,tegra186-pinmux 17 - nvidia,tegra186-pinmux-aon 18 19 reg: 20 items: 21 - description: pinmux registers 22 23patternProperties: 24 "^pinmux(-[a-z0-9-]+)?$": 25 type: object 26 27 # pin groups 28 additionalProperties: 29 $ref: nvidia,tegra-pinmux-common.yaml 30 unevaluatedProperties: false 31 properties: 32 nvidia,function: 33 enum: [ aud, can0, can1, ccla, dca, dcb, dcc, directdc, directdc1, 34 displaya, displayb, dmic1, dmic2, dmic3, dmic4, dmic5, dp, 35 dspk0, dspk1, dtv, eqos, extperiph1, extperiph2, extperiph3, 36 extperiph4, gp, gpio, hdmi, i2c1, i2c2, i2c3, i2c5, i2c7, 37 i2c8, i2c9, i2s1, i2s2, i2s3, i2s4, i2s5, i2s6, iqc0, iqc1, 38 nv, pe, pe0, pe1, pe2, qspi, rsvd0, rsvd1, rsvd2, rsvd3, 39 sata, sce, sdmmc1, sdmmc2, sdmmc3, sdmmc4, soc, spdif, spi1, 40 spi2, spi3, spi4, touch, uarta, uartb, uartc, uartd, uarte, 41 uartf, uartg, ufs0, usb, vgp1, vgp2, vgp3, vgp4, vgp5, vgp6, 42 wdt ] 43 44 nvidia,pull: true 45 nvidia,tristate: true 46 nvidia,schmitt: true 47 nvidia,enable-input: true 48 nvidia,open-drain: true 49 nvidia,lock: true 50 nvidia,drive-type: true 51 nvidia,io-hv: true 52 53 required: 54 - nvidia,pins 55 56additionalProperties: false 57 58allOf: 59 - if: 60 properties: 61 compatible: 62 const: nvidia,tegra186-pinmux 63 then: 64 patternProperties: 65 "^pinmux(-[a-z0-9-]+)?$": 66 type: object 67 additionalProperties: 68 properties: 69 nvidia,pins: 70 description: An array of strings. Each string contains the name 71 of a pin or group. Valid values for these names are listed 72 below. 73 items: 74 enum: [ pex_l0_rst_n_pa0, pex_l0_clkreq_n_pa1, 75 pex_wake_n_pa2, pex_l1_rst_n_pa3, 76 pex_l1_clkreq_n_pa4, pex_l2_rst_n_pa5, 77 pex_l2_clkreq_n_pa6, uart4_tx_pb0, uart4_rx_pb1, 78 uart4_rts_pb2, uart4_cts_pb3, gpio_wan1_pb4, 79 gpio_wan2_pb5, gpio_wan3_pb6, gpio_wan4_pc0, 80 dap2_sclk_pc1, dap2_dout_pc2, dap2_din_pc3, 81 dap2_fs_pc4, gen1_i2c_scl_pc5, gen1_i2c_sda_pc6, 82 sdmmc1_clk_pd0, sdmmc1_cmd_pd1, sdmmc1_dat0_pd2, 83 sdmmc1_dat1_pd3, sdmmc1_dat2_pd4, sdmmc1_dat3_pd5, 84 eqos_txc_pe0, eqos_td0_pe1, eqos_td1_pe2, 85 eqos_td2_pe3, eqos_td3_pe4, eqos_tx_ctl_pe5, 86 eqos_rd0_pe6, eqos_rd1_pe7, eqos_rd2_pf0, 87 eqos_rd3_pf1, eqos_rx_ctl_pf2, eqos_rxc_pf3, 88 eqos_mdio_pf4, eqos_mdc_pf5, sdmmc3_clk_pg0, 89 sdmmc3_cmd_pg1, sdmmc3_dat0_pg2, sdmmc3_dat1_pg3, 90 sdmmc3_dat2_pg4, sdmmc3_dat3_pg5, gpio_wan5_ph0, 91 gpio_wan6_ph1, gpio_wan7_ph2, gpio_wan8_ph3, 92 bcpu_pwr_req_ph4, mcpu_pwr_req_ph5, gpu_pwr_req_ph6, 93 gpio_pq0_pi0, gpio_pq1_pi1, gpio_pq2_pi2, 94 gpio_pq3_pi3, gpio_pq4_pi4, gpio_pq5_pi5, 95 gpio_pq6_pi6, gpio_pq7_pi7, dap1_sclk_pj0, 96 dap1_dout_pj1, dap1_din_pj2, dap1_fs_pj3, 97 aud_mclk_pj4, gpio_aud0_pj5, gpio_aud1_pj6, 98 gpio_aud2_pj7, gpio_aud3_pk0, gen7_i2c_scl_pl0, 99 gen7_i2c_sda_pl1, gen9_i2c_scl_pl2, gen9_i2c_sda_pl3, 100 usb_vbus_en0_pl4, usb_vbus_en1_pl5, gp_pwm6_pl6, 101 gp_pwm7_pl7, dmic1_dat_pm0, dmic1_clk_pm1, 102 dmic2_dat_pm2, dmic2_clk_pm3, dmic4_dat_pm4, 103 dmic4_clk_pm5, gpio_cam1_pn0, gpio_cam2_pn1, 104 gpio_cam3_pn2, gpio_cam4_pn3, gpio_cam6_pn5, 105 gpio_cam7_pn6, extperiph1_clk_po0, 106 extperiph2_clk_po1, cam_i2c_scl_po2, cam_i2c_sda_po3, 107 dp_aux_ch0_hpd_pp0, dp_aux_ch1_hpd_pp1, hdmi_cec_pp2, 108 gpio_edp0_pp3, gpio_edp1_pp4, gpio_edp2_pp5, 109 gpio_edp3_pp6, directdc1_clk_pq0, directdc1_in_pq1, 110 directdc1_out0_pq2, directdc1_out1_pq3, 111 directdc1_out2_pq4, directdc1_out3_pq5, 112 qspi_sck_pr0, qspi_io0_pr1, qspi_io1_pr2, 113 qspi_io2_pr3, qspi_io3_pr4, qspi_cs_n_pr5, 114 uart1_tx_pt0, uart1_rx_pt1, uart1_rts_pt2, 115 uart1_cts_pt3, uart2_tx_px0, uart2_rx_px1, 116 uart2_rts_px2, uart2_cts_px3, uart5_tx_px4, 117 uart5_rx_px5, uart5_rts_px6, uart5_cts_px7, 118 gpio_mdm1_py0, gpio_mdm2_py1, gpio_mdm3_py2, 119 gpio_mdm4_py3, gpio_mdm5_py4, gpio_mdm6_py5, 120 gpio_mdm7_py6, ufs0_ref_clk_pbb0, ufs0_rst_pbb1, 121 dap4_sclk_pcc0, dap4_dout_pcc1, dap4_din_pcc2, 122 dap4_fs_pcc3, directdc_comp, sdmmc1_comp, eqos_comp, 123 sdmmc3_comp, qspi_comp, 124 # drive groups 125 drive_gpio_aud3_pk0, drive_gpio_aud2_pj7, 126 drive_gpio_aud1_pj6, drive_gpio_aud0_pj5, 127 drive_aud_mclk_pj4, drive_dap1_fs_pj3, 128 drive_dap1_din_pj2, drive_dap1_dout_pj1, 129 drive_dap1_sclk_pj0, drive_dmic1_clk_pm1, 130 drive_dmic1_dat_pm0, drive_dmic2_dat_pm2, 131 drive_dmic2_clk_pm3, drive_dmic4_dat_pm4, 132 drive_dmic4_clk_pm5, drive_dap4_fs_pcc3, 133 drive_dap4_din_pcc2, drive_dap4_dout_pcc1, 134 drive_dap4_sclk_pcc0, drive_extperiph2_clk_po1, 135 drive_extperiph1_clk_po0, drive_cam_i2c_sda_po3, 136 drive_cam_i2c_scl_po2, drive_gpio_cam1_pn0, 137 drive_gpio_cam2_pn1, drive_gpio_cam3_pn2, 138 drive_gpio_cam4_pn3, drive_gpio_cam5_pn4, 139 drive_gpio_cam6_pn5, drive_gpio_cam7_pn6, 140 drive_dap2_din_pc3, drive_dap2_dout_pc2, 141 drive_dap2_fs_pc4, drive_dap2_sclk_pc1, 142 drive_uart4_cts_pb3, drive_uart4_rts_pb2, 143 drive_uart4_rx_pb1, drive_uart4_tx_pb0, 144 drive_gpio_wan4_pc0, drive_gpio_wan3_pb6, 145 drive_gpio_wan2_pb5, drive_gpio_wan1_pb4, 146 drive_gen1_i2c_scl_pc5, drive_gen1_i2c_sda_pc6, 147 drive_uart1_cts_pt3, drive_uart1_rts_pt2, 148 drive_uart1_rx_pt1, drive_uart1_tx_pt0, 149 drive_directdc1_out3_pq5, drive_directdc1_out2_pq4, 150 drive_directdc1_out1_pq3, drive_directdc1_out0_pq2, 151 drive_directdc1_in_pq1, drive_directdc1_clk_pq0, 152 drive_gpio_pq0_pi0, drive_gpio_pq1_pi1, 153 drive_gpio_pq2_pi2, drive_gpio_pq3_pi3, 154 drive_gpio_pq4_pi4, drive_gpio_pq5_pi5, 155 drive_gpio_pq6_pi6, drive_gpio_pq7_pi7, 156 drive_gpio_edp2_pp5, drive_gpio_edp3_pp6, 157 drive_gpio_edp0_pp3, drive_gpio_edp1_pp4, 158 drive_dp_aux_ch0_hpd_pp0, drive_dp_aux_ch1_hpd_pp1, 159 drive_hdmi_cec_pp2, drive_pex_l2_clkreq_n_pa6, 160 drive_pex_wake_n_pa2, drive_pex_l1_clkreq_n_pa4, 161 drive_pex_l1_rst_n_pa3, drive_pex_l0_clkreq_n_pa1, 162 drive_pex_l0_rst_n_pa0, drive_pex_l2_rst_n_pa5, 163 drive_sdmmc1_clk_pd0, drive_sdmmc1_cmd_pd1, 164 drive_sdmmc1_dat3_pd5, drive_sdmmc1_dat2_pd4, 165 drive_sdmmc1_dat1_pd3, drive_sdmmc1_dat0_pd2, 166 drive_eqos_td3_pe4, drive_eqos_td2_pe3, 167 drive_eqos_td1_pe2, drive_eqos_td0_pe1, 168 drive_eqos_rd3_pf1, drive_eqos_rd2_pf0, 169 drive_eqos_rd1_pe7, drive_eqos_mdio_pf4, 170 drive_eqos_rd0_pe6, drive_eqos_mdc_pf5, 171 drive_eqos_txc_pe0, drive_eqos_rxc_pf3, 172 drive_eqos_tx_ctl_pe5, drive_eqos_rx_ctl_pf2, 173 drive_sdmmc3_dat3_pg5, drive_sdmmc3_dat2_pg4, 174 drive_sdmmc3_dat1_pg3, drive_sdmmc3_dat0_pg2, 175 drive_sdmmc3_cmd_pg1, drive_sdmmc3_clk_pg0, 176 drive_qspi_io3_pr4, drive_qspi_io2_pr3, 177 drive_qspi_io1_pr2, drive_qspi_io0_pr1, 178 drive_qspi_sck_pr0, drive_qspi_cs_n_pr5, 179 drive_gpio_wan8_ph3, drive_gpio_wan7_ph2, 180 drive_gpio_wan6_ph1, drive_gpio_wan5_ph0, 181 drive_uart2_tx_px0, drive_uart2_rx_px1, 182 drive_uart2_rts_px2, drive_uart2_cts_px3, 183 drive_uart5_rx_px5, drive_uart5_tx_px4, 184 drive_uart5_rts_px6, drive_uart5_cts_px7, 185 drive_gpio_mdm1_py0, drive_gpio_mdm2_py1, 186 drive_gpio_mdm3_py2, drive_gpio_mdm4_py3, 187 drive_gpio_mdm5_py4, drive_gpio_mdm6_py5, 188 drive_gpio_mdm7_py6, drive_bcpu_pwr_req_ph4, 189 drive_mcpu_pwr_req_ph5, drive_gpu_pwr_req_ph6, 190 drive_gen7_i2c_scl_pl0, drive_gen7_i2c_sda_pl1, 191 drive_gen9_i2c_sda_pl3, drive_gen9_i2c_scl_pl2, 192 drive_usb_vbus_en0_pl4, drive_usb_vbus_en1_pl5, 193 drive_gp_pwm7_pl7, drive_gp_pwm6_pl6, 194 drive_ufs0_rst_pbb1, drive_ufs0_ref_clk_pbb0, 195 drive_directdc_comp, drive_sdmmc1_comp, 196 drive_eqos_comp, drive_sdmmc3_comp, drive_sdmmc4_clk, 197 drive_sdmmc4_cmd, drive_sdmmc4_dqs, 198 drive_sdmmc4_dat7, drive_sdmmc4_dat6, 199 drive_sdmmc4_dat5, drive_sdmmc4_dat4, 200 drive_sdmmc4_dat3, drive_sdmmc4_dat2, 201 drive_sdmmc4_dat1, drive_sdmmc4_dat0, 202 drive_qspi_comp ] 203 204 - if: 205 properties: 206 compatible: 207 const: nvidia,tegra186-pinmux-aon 208 then: 209 patternProperties: 210 "^pinmux(-[a-z0-9-]+)?$": 211 type: object 212 additionalProperties: 213 properties: 214 nvidia,pins: 215 items: 216 enum: [ pwr_i2c_scl_ps0, pwr_i2c_sda_ps1, batt_oc_ps2, 217 safe_state_ps3, vcomp_alert_ps4, gpio_dis0_pu0, 218 gpio_dis1_pu1, gpio_dis2_pu2, gpio_dis3_pu3, 219 gpio_dis4_pu4, gpio_dis5_pu5, gpio_sen0_pv0, 220 gpio_sen1_pv1, gpio_sen2_pv2, gpio_sen3_pv3, 221 gpio_sen4_pv4, gpio_sen5_pv5, gpio_sen6_pv6, 222 gpio_sen7_pv7, gen8_i2c_scl_pw0, gen8_i2c_sda_pw1, 223 uart3_tx_pw2, uart3_rx_pw3, uart3_rts_pw4, 224 uart3_cts_pw5, uart7_tx_pw6, uart7_rx_pw7, 225 can1_dout_pz0, can1_din_pz1, can0_dout_pz2, 226 can0_din_pz3, can_gpio0_paa0, can_gpio1_paa1, 227 can_gpio2_paa2, can_gpio3_paa3, can_gpio4_paa4, 228 can_gpio5_paa5, can_gpio6_paa6, can_gpio7_paa7, 229 gpio_sen8_pee0, gpio_sen9_pee1, touch_clk_pee2, 230 power_on_pff0, gpio_sw1_pff1, gpio_sw2_pff2, 231 gpio_sw3_pff3, gpio_sw4_pff4, shutdown, pmu_int, 232 soc_pwr_req, clk_32k_in, 233 # drive groups 234 drive_touch_clk_pee2, drive_uart3_cts_pw5, 235 drive_uart3_rts_pw4, drive_uart3_rx_pw3, 236 drive_uart3_tx_pw2, drive_gen8_i2c_sda_pw1, 237 drive_gen8_i2c_scl_pw0, drive_uart7_rx_pw7, 238 drive_uart7_tx_pw6, drive_gpio_sen0_pv0, 239 drive_gpio_sen1_pv1, drive_gpio_sen2_pv2, 240 drive_gpio_sen3_pv3, drive_gpio_sen4_pv4, 241 drive_gpio_sen5_pv5, drive_gpio_sen6_pv6, 242 drive_gpio_sen7_pv7, drive_gpio_sen8_pee0, 243 drive_gpio_sen9_pee1, drive_can_gpio7_paa7, 244 drive_can1_dout_pz0, drive_can1_din_pz1, 245 drive_can0_dout_pz2, drive_can0_din_pz3, 246 drive_can_gpio0_paa0, drive_can_gpio1_paa1, 247 drive_can_gpio2_paa2, drive_can_gpio3_paa3, 248 drive_can_gpio4_paa4, drive_can_gpio5_paa5, 249 drive_can_gpio6_paa6, drive_gpio_sw1_pff1, 250 drive_gpio_sw2_pff2, drive_gpio_sw3_pff3, 251 drive_gpio_sw4_pff4, drive_shutdown, drive_pmu_int, 252 drive_safe_state_ps3, drive_vcomp_alert_ps4, 253 drive_soc_pwr_req, drive_batt_oc_ps2, 254 drive_clk_32k_in, drive_power_on_pff0, 255 drive_pwr_i2c_scl_ps0, drive_pwr_i2c_sda_ps1, 256 drive_gpio_dis0_pu0, drive_gpio_dis1_pu1, 257 drive_gpio_dis2_pu2, drive_gpio_dis3_pu3, 258 drive_gpio_dis4_pu4, drive_gpio_dis5_pu5 ] 259 260required: 261 - compatible 262 - reg 263 264examples: 265 - | 266 #include <dt-bindings/pinctrl/pinctrl-tegra.h> 267 268 pinmux@2430000 { 269 compatible = "nvidia,tegra186-pinmux"; 270 reg = <0x2430000 0x15000>; 271 272 pinctrl-names = "jetson_io"; 273 pinctrl-0 = <&jetson_io_pinmux>; 274 275 jetson_io_pinmux: pinmux { 276 hdr40-pin7 { 277 nvidia,pins = "aud_mclk_pj4"; 278 nvidia,function = "aud"; 279 nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 280 nvidia,tristate = <TEGRA_PIN_DISABLE>; 281 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 282 }; 283 }; 284 }; 285... 286