xref: /linux/Documentation/devicetree/bindings/pinctrl/nvidia,tegra124-xusb-padctl.txt (revision ca55b2fef3a9373fcfc30f82fd26bc7fccbda732) 
1Device tree binding for NVIDIA Tegra XUSB pad controller
2========================================================
3
4The Tegra XUSB pad controller manages a set of lanes, each of which can be
5assigned to one out of a set of different pads. Some of these pads have an
6associated PHY that must be powered up before the pad can be used.
7
8This document defines the device-specific binding for the XUSB pad controller.
9
10Refer to pinctrl-bindings.txt in this directory for generic information about
11pin controller device tree bindings and ../phy/phy-bindings.txt for details on
12how to describe and reference PHYs in device trees.
13
14Required properties:
15--------------------
16- compatible: For Tegra124, must contain "nvidia,tegra124-xusb-padctl".
17  Otherwise, must contain '"nvidia,<chip>-xusb-padctl",
18  "nvidia-tegra124-xusb-padctl"', where <chip> is tegra132 or tegra210.
19- reg: Physical base address and length of the controller's registers.
20- resets: Must contain an entry for each entry in reset-names.
21  See ../reset/reset.txt for details.
22- reset-names: Must include the following entries:
23  - padctl
24- #phy-cells: Should be 1. The specifier is the index of the PHY to reference.
25  See <dt-bindings/pinctrl/pinctrl-tegra-xusb.h> for the list of valid values.
26
27Lane muxing:
28------------
29
30Child nodes contain the pinmux configurations following the conventions from
31the pinctrl-bindings.txt document. Typically a single, static configuration is
32given and applied at boot time.
33
34Each subnode describes groups of lanes along with parameters and pads that
35they should be assigned to. The name of these subnodes is not important. All
36subnodes should be parsed solely based on their content.
37
38Each subnode only applies the parameters that are explicitly listed. In other
39words, if a subnode that lists a function but no pin configuration parameters
40implies no information about any pin configuration parameters. Similarly, a
41subnode that describes only an IDDQ parameter implies no information about
42what function the pins are assigned to. For this reason even seemingly boolean
43values are actually tristates in this binding: unspecified, off or on.
44Unspecified is represented as an absent property, and off/on are represented
45as integer values 0 and 1.
46
47Required properties:
48- nvidia,lanes: An array of strings. Each string is the name of a lane.
49
50Optional properties:
51- nvidia,function: A string that is the name of the function (pad) that the
52  pin or group should be assigned to. Valid values for function names are
53  listed below.
54- nvidia,iddq: Enables IDDQ mode of the lane. (0: no, 1: yes)
55
56Note that not all of these properties are valid for all lanes. Lanes can be
57divided into three groups:
58
59  - otg-0, otg-1, otg-2:
60
61    Valid functions for this group are: "snps", "xusb", "uart", "rsvd".
62
63    The nvidia,iddq property does not apply to this group.
64
65  - ulpi-0, hsic-0, hsic-1:
66
67    Valid functions for this group are: "snps", "xusb".
68
69    The nvidia,iddq property does not apply to this group.
70
71  - pcie-0, pcie-1, pcie-2, pcie-3, pcie-4, sata-0:
72
73    Valid functions for this group are: "pcie", "usb3", "sata", "rsvd".
74
75
76Example:
77========
78
79SoC file extract:
80-----------------
81
82	padctl@0,7009f000 {
83		compatible = "nvidia,tegra124-xusb-padctl";
84		reg = <0x0 0x7009f000 0x0 0x1000>;
85		resets = <&tegra_car 142>;
86		reset-names = "padctl";
87
88		#phy-cells = <1>;
89	};
90
91Board file extract:
92-------------------
93
94	pcie-controller@0,01003000 {
95		...
96
97		phys = <&padctl 0>;
98		phy-names = "pcie";
99
100		...
101	};
102
103	...
104
105	padctl: padctl@0,7009f000 {
106		pinctrl-0 = <&padctl_default>;
107		pinctrl-names = "default";
108
109		padctl_default: pinmux {
110			usb3 {
111				nvidia,lanes = "pcie-0", "pcie-1";
112				nvidia,function = "usb3";
113				nvidia,iddq = <0>;
114			};
115
116			pcie {
117				nvidia,lanes = "pcie-2", "pcie-3",
118					       "pcie-4";
119				nvidia,function = "pcie";
120				nvidia,iddq = <0>;
121			};
122
123			sata {
124				nvidia,lanes = "sata-0";
125				nvidia,function = "sata";
126				nvidia,iddq = <0>;
127			};
128		};
129	};
130