1*645f1095SConor Dooley# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause 2*645f1095SConor Dooley%YAML 1.2 3*645f1095SConor Dooley--- 4*645f1095SConor Dooley$id: http://devicetree.org/schemas/pinctrl/microchip,pic64gx-pinctrl-gpio2.yaml# 5*645f1095SConor Dooley$schema: http://devicetree.org/meta-schemas/core.yaml# 6*645f1095SConor Dooley 7*645f1095SConor Dooleytitle: Microchip PIC64GX GPIO2 Mux 8*645f1095SConor Dooley 9*645f1095SConor Dooleymaintainers: 10*645f1095SConor Dooley - Conor Dooley <conor.dooley@microchip.com> 11*645f1095SConor Dooley 12*645f1095SConor Dooleydescription: 13*645f1095SConor Dooley The "GPIO2 Mux" determines whether GPIO2 or select other functions are 14*645f1095SConor Dooley available on package pins on PIC64GX. Some of these functions must be 15*645f1095SConor Dooley mapped to this mux via iomux0 for settings here to have any impact. 16*645f1095SConor Dooley 17*645f1095SConor Dooleyproperties: 18*645f1095SConor Dooley compatible: 19*645f1095SConor Dooley const: microchip,pic64gx-pinctrl-gpio2 20*645f1095SConor Dooley 21*645f1095SConor Dooley reg: 22*645f1095SConor Dooley maxItems: 1 23*645f1095SConor Dooley 24*645f1095SConor Dooley pinctrl-use-default: true 25*645f1095SConor Dooley 26*645f1095SConor DooleypatternProperties: 27*645f1095SConor Dooley '^mux-': 28*645f1095SConor Dooley type: object 29*645f1095SConor Dooley $ref: pinmux-node.yaml 30*645f1095SConor Dooley additionalProperties: false 31*645f1095SConor Dooley 32*645f1095SConor Dooley properties: 33*645f1095SConor Dooley function: 34*645f1095SConor Dooley description: 35*645f1095SConor Dooley A string containing the name of the function to mux to the group. 36*645f1095SConor Dooley enum: [ mdio0, mdio1, spi0, can0, pcie, qspi, uart3, uart4, can1, uart2, gpio ] 37*645f1095SConor Dooley 38*645f1095SConor Dooley groups: 39*645f1095SConor Dooley description: 40*645f1095SConor Dooley An array of strings. Each string contains the name of a group. 41*645f1095SConor Dooley items: 42*645f1095SConor Dooley enum: [ mdio0, mdio1, spi0, can0, pcie, qspi, uart3, uart4, can1, uart2, 43*645f1095SConor Dooley gpio_mdio0, gpio_mdio1, gpio_spi0, gpio_can0, gpio_pcie, 44*645f1095SConor Dooley gpio_qspi, gpio_uart3, gpio_uart4, gpio_can1, gpio_uart2 ] 45*645f1095SConor Dooley 46*645f1095SConor Dooley required: 47*645f1095SConor Dooley - function 48*645f1095SConor Dooley - groups 49*645f1095SConor Dooley 50*645f1095SConor Dooleyrequired: 51*645f1095SConor Dooley - compatible 52*645f1095SConor Dooley - reg 53*645f1095SConor Dooley 54*645f1095SConor DooleyadditionalProperties: false 55*645f1095SConor Dooley 56*645f1095SConor Dooleyexamples: 57*645f1095SConor Dooley - | 58*645f1095SConor Dooley pinctrl@41000000 { 59*645f1095SConor Dooley compatible = "microchip,pic64gx-pinctrl-gpio2"; 60*645f1095SConor Dooley reg = <0x41000000 0x4>; 61*645f1095SConor Dooley pinctrl-use-default; 62*645f1095SConor Dooley pinctrl-names = "default"; 63*645f1095SConor Dooley pinctrl-0 = <&mdio0_gpio2>, <&mdio1_gpio2>, <&spi0_gpio2>, <&qspi_gpio2>, 64*645f1095SConor Dooley <&uart3_gpio2>, <&uart4_gpio2>, <&can1_gpio2>, <&can0_gpio2>, 65*645f1095SConor Dooley <&uart2_gpio2>; 66*645f1095SConor Dooley 67*645f1095SConor Dooley mux-gpio2 { 68*645f1095SConor Dooley function = "gpio"; 69*645f1095SConor Dooley groups = "gpio_mdio1", "gpio_spi0", "gpio_can0", "gpio_pcie", 70*645f1095SConor Dooley "gpio_qspi", "gpio_uart3", "gpio_uart4", "gpio_can1"; 71*645f1095SConor Dooley }; 72*645f1095SConor Dooley }; 73*645f1095SConor Dooley 74*645f1095SConor Dooley... 75