xref: /linux/Documentation/devicetree/bindings/pinctrl/microchip,mcp23s08.yaml (revision 2d32fba02e0e5b67fb3a4ea51dde80c0db83f1c1)
1*3ad8d3ecSHimanshu Bhavani# SPDX-License-Identifier: GPL-2.0-only
2*3ad8d3ecSHimanshu Bhavani%YAML 1.2
3*3ad8d3ecSHimanshu Bhavani---
4*3ad8d3ecSHimanshu Bhavani$id: http://devicetree.org/schemas/pinctrl/microchip,mcp23s08.yaml#
5*3ad8d3ecSHimanshu Bhavani$schema: http://devicetree.org/meta-schemas/core.yaml#
6*3ad8d3ecSHimanshu Bhavani
7*3ad8d3ecSHimanshu Bhavanititle: Microchip I/O expander with serial interface (I2C/SPI)
8*3ad8d3ecSHimanshu Bhavani
9*3ad8d3ecSHimanshu Bhavanimaintainers:
10*3ad8d3ecSHimanshu Bhavani  - Himanshu Bhavani <himanshu.bhavani@siliconsignals.io>
11*3ad8d3ecSHimanshu Bhavani
12*3ad8d3ecSHimanshu Bhavanidescription:
13*3ad8d3ecSHimanshu Bhavani  Microchip MCP23008, MCP23017, MCP23S08, MCP23S17, MCP23S18 GPIO expander
14*3ad8d3ecSHimanshu Bhavani  chips.These chips provide 8 or 16 GPIO pins with either I2C or SPI interface.
15*3ad8d3ecSHimanshu Bhavani
16*3ad8d3ecSHimanshu BhavaniallOf:
17*3ad8d3ecSHimanshu Bhavani  - $ref: /schemas/spi/spi-peripheral-props.yaml#
18*3ad8d3ecSHimanshu Bhavani
19*3ad8d3ecSHimanshu Bhavaniproperties:
20*3ad8d3ecSHimanshu Bhavani  compatible:
21*3ad8d3ecSHimanshu Bhavani    enum:
22*3ad8d3ecSHimanshu Bhavani      - microchip,mcp23s08
23*3ad8d3ecSHimanshu Bhavani      - microchip,mcp23s17
24*3ad8d3ecSHimanshu Bhavani      - microchip,mcp23s18
25*3ad8d3ecSHimanshu Bhavani      - microchip,mcp23008
26*3ad8d3ecSHimanshu Bhavani      - microchip,mcp23017
27*3ad8d3ecSHimanshu Bhavani      - microchip,mcp23018
28*3ad8d3ecSHimanshu Bhavani
29*3ad8d3ecSHimanshu Bhavani  reg:
30*3ad8d3ecSHimanshu Bhavani    maxItems: 1
31*3ad8d3ecSHimanshu Bhavani
32*3ad8d3ecSHimanshu Bhavani  gpio-controller: true
33*3ad8d3ecSHimanshu Bhavani
34*3ad8d3ecSHimanshu Bhavani  '#gpio-cells':
35*3ad8d3ecSHimanshu Bhavani    const: 2
36*3ad8d3ecSHimanshu Bhavani
37*3ad8d3ecSHimanshu Bhavani  interrupt-controller: true
38*3ad8d3ecSHimanshu Bhavani
39*3ad8d3ecSHimanshu Bhavani  '#interrupt-cells':
40*3ad8d3ecSHimanshu Bhavani    const: 2
41*3ad8d3ecSHimanshu Bhavani
42*3ad8d3ecSHimanshu Bhavani  interrupts:
43*3ad8d3ecSHimanshu Bhavani    maxItems: 1
44*3ad8d3ecSHimanshu Bhavani
45*3ad8d3ecSHimanshu Bhavani  reset-gpios:
46*3ad8d3ecSHimanshu Bhavani    description: GPIO specifier for active-low reset pin.
47*3ad8d3ecSHimanshu Bhavani    maxItems: 1
48*3ad8d3ecSHimanshu Bhavani
49*3ad8d3ecSHimanshu Bhavani  microchip,spi-present-mask:
50*3ad8d3ecSHimanshu Bhavani    description:
51*3ad8d3ecSHimanshu Bhavani      Multiple SPI chips can share the same SPI chipselect. Set a bit in
52*3ad8d3ecSHimanshu Bhavani      bit0-7 in this mask to 1 if there is a chip connected with the
53*3ad8d3ecSHimanshu Bhavani      corresponding spi address set. For example if you have a chip with
54*3ad8d3ecSHimanshu Bhavani      address 3 connected, you have to set bit3 to 1, which is 0x08. mcp23s08
55*3ad8d3ecSHimanshu Bhavani      chip variant only supports bits 0-3. It is not possible to mix mcp23s08
56*3ad8d3ecSHimanshu Bhavani      and mcp23s17 on the same chipselect. Set at least one bit to 1 for SPI
57*3ad8d3ecSHimanshu Bhavani      chips.
58*3ad8d3ecSHimanshu Bhavani    $ref: /schemas/types.yaml#/definitions/uint8
59*3ad8d3ecSHimanshu Bhavani
60*3ad8d3ecSHimanshu Bhavani  microchip,irq-mirror:
61*3ad8d3ecSHimanshu Bhavani    type: boolean
62*3ad8d3ecSHimanshu Bhavani    description:
63*3ad8d3ecSHimanshu Bhavani      Sets the mirror flag in the IOCON register. Devices with two interrupt
64*3ad8d3ecSHimanshu Bhavani      outputs (these are the devices ending with 17 and those that have 16 IOs)
65*3ad8d3ecSHimanshu Bhavani      have two IO banks IO 0-7 form bank 1 and IO 8-15 are bank 2. These chips
66*3ad8d3ecSHimanshu Bhavani      have two different interrupt outputs One for bank 1 and another for
67*3ad8d3ecSHimanshu Bhavani      bank 2. If irq-mirror is set, both interrupts are generated regardless of
68*3ad8d3ecSHimanshu Bhavani      the bank that an input change occurred on. If it is not set,the interrupt
69*3ad8d3ecSHimanshu Bhavani      are only generated for the bank they belong to.
70*3ad8d3ecSHimanshu Bhavani
71*3ad8d3ecSHimanshu Bhavani  microchip,irq-active-high:
72*3ad8d3ecSHimanshu Bhavani    type: boolean
73*3ad8d3ecSHimanshu Bhavani    description:
74*3ad8d3ecSHimanshu Bhavani      Sets the INTPOL flag in the IOCON register.This configures the IRQ output
75*3ad8d3ecSHimanshu Bhavani      polarity as active high.
76*3ad8d3ecSHimanshu Bhavani
77*3ad8d3ecSHimanshu Bhavani  drive-open-drain:
78*3ad8d3ecSHimanshu Bhavani    type: boolean
79*3ad8d3ecSHimanshu Bhavani    description:
80*3ad8d3ecSHimanshu Bhavani      Sets the ODR flag in the IOCON register. This configures the IRQ output as
81*3ad8d3ecSHimanshu Bhavani      open drain active low.
82*3ad8d3ecSHimanshu Bhavani
83*3ad8d3ecSHimanshu Bhavani  pinmux:
84*3ad8d3ecSHimanshu Bhavani    type: object
85*3ad8d3ecSHimanshu Bhavani    properties:
86*3ad8d3ecSHimanshu Bhavani      pins:
87*3ad8d3ecSHimanshu Bhavani        description:
88*3ad8d3ecSHimanshu Bhavani          The list of GPIO pins controlled by this node. Each pin name
89*3ad8d3ecSHimanshu Bhavani          corresponds to a physical pin on the GPIO expander.
90*3ad8d3ecSHimanshu Bhavani        items:
91*3ad8d3ecSHimanshu Bhavani          pattern: '^gpio([0-9]|[1][0-5])$'
92*3ad8d3ecSHimanshu Bhavani        maxItems: 16
93*3ad8d3ecSHimanshu Bhavani
94*3ad8d3ecSHimanshu Bhavani      bias-pull-up:
95*3ad8d3ecSHimanshu Bhavani        type: boolean
96*3ad8d3ecSHimanshu Bhavani        description:
97*3ad8d3ecSHimanshu Bhavani          Configures pull-up resistors for the GPIO pins. Absence of this
98*3ad8d3ecSHimanshu Bhavani          property will leave the configuration in its default state.
99*3ad8d3ecSHimanshu Bhavani
100*3ad8d3ecSHimanshu Bhavani    required:
101*3ad8d3ecSHimanshu Bhavani      - pins
102*3ad8d3ecSHimanshu Bhavani
103*3ad8d3ecSHimanshu Bhavani    additionalProperties: false
104*3ad8d3ecSHimanshu Bhavani
105*3ad8d3ecSHimanshu Bhavanirequired:
106*3ad8d3ecSHimanshu Bhavani  - compatible
107*3ad8d3ecSHimanshu Bhavani  - reg
108*3ad8d3ecSHimanshu Bhavani  - gpio-controller
109*3ad8d3ecSHimanshu Bhavani  - '#gpio-cells'
110*3ad8d3ecSHimanshu Bhavani
111*3ad8d3ecSHimanshu BhavaniunevaluatedProperties: false
112*3ad8d3ecSHimanshu Bhavani
113*3ad8d3ecSHimanshu Bhavaniexamples:
114*3ad8d3ecSHimanshu Bhavani  - |
115*3ad8d3ecSHimanshu Bhavani    #include <dt-bindings/interrupt-controller/irq.h>
116*3ad8d3ecSHimanshu Bhavani    #include <dt-bindings/gpio/gpio.h>
117*3ad8d3ecSHimanshu Bhavani
118*3ad8d3ecSHimanshu Bhavani    i2c {
119*3ad8d3ecSHimanshu Bhavani        #address-cells = <1>;
120*3ad8d3ecSHimanshu Bhavani        #size-cells = <0>;
121*3ad8d3ecSHimanshu Bhavani
122*3ad8d3ecSHimanshu Bhavani        gpio@21 {
123*3ad8d3ecSHimanshu Bhavani            compatible = "microchip,mcp23017";
124*3ad8d3ecSHimanshu Bhavani            reg = <0x21>;
125*3ad8d3ecSHimanshu Bhavani            gpio-controller;
126*3ad8d3ecSHimanshu Bhavani            #gpio-cells = <2>;
127*3ad8d3ecSHimanshu Bhavani
128*3ad8d3ecSHimanshu Bhavani            interrupt-parent = <&gpio1>;
129*3ad8d3ecSHimanshu Bhavani            interrupts = <17 IRQ_TYPE_LEVEL_LOW>;
130*3ad8d3ecSHimanshu Bhavani            interrupt-controller;
131*3ad8d3ecSHimanshu Bhavani            #interrupt-cells = <2>;
132*3ad8d3ecSHimanshu Bhavani
133*3ad8d3ecSHimanshu Bhavani            microchip,irq-mirror;
134*3ad8d3ecSHimanshu Bhavani            pinctrl-names = "default";
135*3ad8d3ecSHimanshu Bhavani            pinctrl-0 = <&pinctrl_i2c_gpio0>, <&gpiopullups>;
136*3ad8d3ecSHimanshu Bhavani            reset-gpios = <&gpio6 15 GPIO_ACTIVE_LOW>;
137*3ad8d3ecSHimanshu Bhavani
138*3ad8d3ecSHimanshu Bhavani            gpiopullups: pinmux {
139*3ad8d3ecSHimanshu Bhavani                pins = "gpio0", "gpio1", "gpio2", "gpio3",
140*3ad8d3ecSHimanshu Bhavani                       "gpio4", "gpio5", "gpio6", "gpio7",
141*3ad8d3ecSHimanshu Bhavani                       "gpio8", "gpio9", "gpio10", "gpio11",
142*3ad8d3ecSHimanshu Bhavani                       "gpio12", "gpio13", "gpio14", "gpio15";
143*3ad8d3ecSHimanshu Bhavani                bias-pull-up;
144*3ad8d3ecSHimanshu Bhavani            };
145*3ad8d3ecSHimanshu Bhavani        };
146*3ad8d3ecSHimanshu Bhavani    };
147*3ad8d3ecSHimanshu Bhavani
148*3ad8d3ecSHimanshu Bhavani  - |
149*3ad8d3ecSHimanshu Bhavani    spi {
150*3ad8d3ecSHimanshu Bhavani        #address-cells = <1>;
151*3ad8d3ecSHimanshu Bhavani        #size-cells = <0>;
152*3ad8d3ecSHimanshu Bhavani
153*3ad8d3ecSHimanshu Bhavani        gpio@0 {
154*3ad8d3ecSHimanshu Bhavani            compatible = "microchip,mcp23s17";
155*3ad8d3ecSHimanshu Bhavani            reg = <0>;
156*3ad8d3ecSHimanshu Bhavani            gpio-controller;
157*3ad8d3ecSHimanshu Bhavani            #gpio-cells = <2>;
158*3ad8d3ecSHimanshu Bhavani            spi-max-frequency = <1000000>;
159*3ad8d3ecSHimanshu Bhavani            microchip,spi-present-mask = /bits/ 8 <0x01>;
160*3ad8d3ecSHimanshu Bhavani        };
161*3ad8d3ecSHimanshu Bhavani    };
162