1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2%YAML 1.2 3--- 4$id: http://devicetree.org/schemas/pinctrl/mediatek,mt8365-pinctrl.yaml# 5$schema: http://devicetree.org/meta-schemas/core.yaml# 6 7title: Mediatek MT8365 Pin Controller 8 9maintainers: 10 - Zhiyong Tao <zhiyong.tao@mediatek.com> 11 - Bernhard Rosenkränzer <bero@baylibre.com> 12 13description: | 14 The MediaTek's MT8365 Pin controller is used to control SoC pins. 15 16properties: 17 compatible: 18 const: mediatek,mt8365-pinctrl 19 20 reg: 21 maxItems: 1 22 23 mediatek,pctl-regmap: 24 $ref: /schemas/types.yaml#/definitions/phandle-array 25 items: 26 maxItems: 1 27 minItems: 1 28 maxItems: 2 29 description: | 30 Should be phandles of the syscfg node. 31 32 gpio-controller: true 33 34 "#gpio-cells": 35 const: 2 36 description: | 37 Number of cells in GPIO specifier. Since the generic GPIO 38 binding is used, the amount of cells must be specified as 2. See the below 39 mentioned gpio binding representation for description of particular cells. 40 41 interrupt-controller: true 42 43 interrupts: 44 maxItems: 1 45 46 "#interrupt-cells": 47 const: 2 48 49patternProperties: 50 "-pins$": 51 type: object 52 additionalProperties: false 53 patternProperties: 54 "pins$": 55 type: object 56 additionalProperties: false 57 description: | 58 A pinctrl node should contain at least one subnode representing the 59 pinctrl groups available on the machine. Each subnode will list the 60 pins it needs, and how they should be configured, with regard to muxer 61 configuration, pullups, drive strength, input enable/disable and input 62 schmitt. 63 $ref: /schemas/pinctrl/pincfg-node.yaml 64 65 properties: 66 pinmux: 67 description: 68 integer array, represents gpio pin number and mux setting. 69 Supported pin number and mux varies for different SoCs, and are 70 defined as macros in <soc>-pinfunc.h directly. 71 72 bias-disable: true 73 74 bias-pull-up: 75 description: | 76 Besides generic pinconfig options, it can be used as the pull up 77 settings for 2 pull resistors, R0 and R1. User can configure those 78 special pins. 79 80 bias-pull-down: true 81 82 input-enable: true 83 84 input-disable: true 85 86 output-low: true 87 88 output-high: true 89 90 input-schmitt-enable: true 91 92 input-schmitt-disable: true 93 94 mediatek,drive-strength-adv: 95 description: | 96 Describe the specific driving setup property. 97 For I2C pins, the existing generic driving setup can only support 98 2/4/6/8/10/12/14/16mA driving. But in specific driving setup, they 99 can support 0.125/0.25/0.5/1mA adjustment. If we enable specific 100 driving setup, the existing generic setup will be disabled. 101 The specific driving setup is controlled by E1E0EN. 102 When E1=0/E0=0, the strength is 0.125mA. 103 When E1=0/E0=1, the strength is 0.25mA. 104 When E1=1/E0=0, the strength is 0.5mA. 105 When E1=1/E0=1, the strength is 1mA. 106 EN is used to enable or disable the specific driving setup. 107 Valid arguments are described as below: 108 0: (E1, E0, EN) = (0, 0, 0) 109 1: (E1, E0, EN) = (0, 0, 1) 110 2: (E1, E0, EN) = (0, 1, 0) 111 3: (E1, E0, EN) = (0, 1, 1) 112 4: (E1, E0, EN) = (1, 0, 0) 113 5: (E1, E0, EN) = (1, 0, 1) 114 6: (E1, E0, EN) = (1, 1, 0) 115 7: (E1, E0, EN) = (1, 1, 1) 116 So the valid arguments are from 0 to 7. 117 $ref: /schemas/types.yaml#/definitions/uint32 118 enum: [0, 1, 2, 3, 4, 5, 6, 7] 119 120 mediatek,pull-up-adv: 121 description: | 122 Pull up setings for 2 pull resistors, R0 and R1. User can 123 configure those special pins. Valid arguments are described as below: 124 0: (R1, R0) = (0, 0) which means R1 disabled and R0 disabled. 125 1: (R1, R0) = (0, 1) which means R1 disabled and R0 enabled. 126 2: (R1, R0) = (1, 0) which means R1 enabled and R0 disabled. 127 3: (R1, R0) = (1, 1) which means R1 enabled and R0 enabled. 128 $ref: /schemas/types.yaml#/definitions/uint32 129 enum: [0, 1, 2, 3] 130 131 mediatek,pull-down-adv: 132 description: | 133 Pull down settings for 2 pull resistors, R0 and R1. User can 134 configure those special pins. Valid arguments are described as below: 135 0: (R1, R0) = (0, 0) which means R1 disabled and R0 disabled. 136 1: (R1, R0) = (0, 1) which means R1 disabled and R0 enabled. 137 2: (R1, R0) = (1, 0) which means R1 enabled and R0 disabled. 138 3: (R1, R0) = (1, 1) which means R1 enabled and R0 enabled. 139 $ref: /schemas/types.yaml#/definitions/uint32 140 enum: [0, 1, 2, 3] 141 142 mediatek,tdsel: 143 description: | 144 An integer describing the steps for output level shifter duty 145 cycle when asserted (high pulse width adjustment). Valid arguments 146 are from 0 to 15. 147 $ref: /schemas/types.yaml#/definitions/uint32 148 149 mediatek,rdsel: 150 description: | 151 An integer describing the steps for input level shifter duty cycle 152 when asserted (high pulse width adjustment). Valid arguments are 153 from 0 to 63. 154 $ref: /schemas/types.yaml#/definitions/uint32 155 156 required: 157 - pinmux 158 159required: 160 - compatible 161 - reg 162 - gpio-controller 163 - "#gpio-cells" 164 165allOf: 166 - $ref: pinctrl.yaml# 167 168additionalProperties: false 169 170examples: 171 - | 172 #include <dt-bindings/interrupt-controller/arm-gic.h> 173 #include <dt-bindings/pinctrl/mt8365-pinfunc.h> 174 soc { 175 #address-cells = <2>; 176 #size-cells = <2>; 177 178 pio: pinctrl@1000b000 { 179 compatible = "mediatek,mt8365-pinctrl"; 180 reg = <0 0x1000b000 0 0x1000>; 181 mediatek,pctl-regmap = <&syscfg_pctl>; 182 gpio-controller; 183 #gpio-cells = <2>; 184 interrupt-controller; 185 #interrupt-cells = <2>; 186 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>; 187 188 pio-pins { 189 pins { 190 pinmux = <MT8365_PIN_59_SDA1__FUNC_SDA1_0>, <MT8365_PIN_60_SCL1__FUNC_SCL1_0>; 191 mediatek,pull-up-adv = <3>; 192 mediatek,drive-strength-adv = <00>; 193 bias-pull-up; 194 }; 195 }; 196 }; 197 }; 198