1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2%YAML 1.2 3--- 4$id: http://devicetree.org/schemas/pinctrl/mediatek,mt8183-pinctrl.yaml# 5$schema: http://devicetree.org/meta-schemas/core.yaml# 6 7title: MediaTek MT8183 Pin Controller 8 9maintainers: 10 - Sean Wang <sean.wang@kernel.org> 11 12description: 13 The MediaTek's MT8183 Pin controller is used to control SoC pins. 14 15properties: 16 compatible: 17 const: mediatek,mt8183-pinctrl 18 19 reg: 20 minItems: 10 21 maxItems: 10 22 23 reg-names: 24 items: 25 - const: iocfg0 26 - const: iocfg1 27 - const: iocfg2 28 - const: iocfg3 29 - const: iocfg4 30 - const: iocfg5 31 - const: iocfg6 32 - const: iocfg7 33 - const: iocfg8 34 - const: eint 35 36 gpio-controller: true 37 38 "#gpio-cells": 39 const: 2 40 description: 41 Number of cells in GPIO specifier. Since the generic GPIO binding is used, 42 the amount of cells must be specified as 2. See the below mentioned gpio 43 binding representation for description of particular cells. 44 45 gpio-ranges: 46 minItems: 1 47 maxItems: 5 48 description: 49 GPIO valid number range. 50 51 gpio-line-names: true 52 53 interrupt-controller: true 54 55 interrupts: 56 maxItems: 1 57 58 "#interrupt-cells": 59 const: 2 60 61allOf: 62 - $ref: pinctrl.yaml# 63 64required: 65 - compatible 66 - reg 67 - gpio-controller 68 - "#gpio-cells" 69 - gpio-ranges 70 71patternProperties: 72 '-pins(-[a-z]+)?$': 73 type: object 74 additionalProperties: false 75 patternProperties: 76 '^pins': 77 type: object 78 additionalProperties: false 79 description: 80 A pinctrl node should contain at least one subnodes representing the 81 pinctrl groups available on the machine. Each subnode will list the 82 pins it needs, and how they should be configured, with regard to muxer 83 configuration, pullups, drive strength, input enable/disable and input 84 schmitt. 85 $ref: /schemas/pinctrl/pincfg-node.yaml 86 87 properties: 88 pinmux: 89 description: 90 Integer array, represents gpio pin number and mux setting. 91 Supported pin number and mux varies for different SoCs, and are 92 defined as macros in <soc>-pinfunc.h directly. 93 94 bias-disable: true 95 96 bias-pull-up: true 97 98 bias-pull-down: true 99 100 input-enable: true 101 102 input-disable: true 103 104 output-low: true 105 106 output-high: true 107 108 input-schmitt-enable: true 109 110 input-schmitt-disable: true 111 112 drive-strength: 113 enum: [2, 4, 6, 8, 10, 12, 14, 16] 114 115 drive-strength-microamp: 116 enum: [125, 250, 500, 1000] 117 118 mediatek,drive-strength-adv: 119 deprecated: true 120 description: | 121 DEPRECATED: Please use drive-strength-microamp instead. 122 Describe the specific driving setup property. 123 For I2C pins, the existing generic driving setup can only support 124 2/4/6/8/10/12/14/16mA driving. But in specific driving setup, they 125 can support 0.125/0.25/0.5/1mA adjustment. If we enable specific 126 driving setup, the existing generic setup will be disabled. 127 The specific driving setup is controlled by E1E0EN. 128 When E1=0/E0=0, the strength is 0.125mA. 129 When E1=0/E0=1, the strength is 0.25mA. 130 When E1=1/E0=0, the strength is 0.5mA. 131 When E1=1/E0=1, the strength is 1mA. 132 EN is used to enable or disable the specific driving setup. 133 Valid arguments are described as below: 134 0: (E1, E0, EN) = (0, 0, 0) 135 1: (E1, E0, EN) = (0, 0, 1) 136 2: (E1, E0, EN) = (0, 1, 0) 137 3: (E1, E0, EN) = (0, 1, 1) 138 4: (E1, E0, EN) = (1, 0, 0) 139 5: (E1, E0, EN) = (1, 0, 1) 140 6: (E1, E0, EN) = (1, 1, 0) 141 7: (E1, E0, EN) = (1, 1, 1) 142 So the valid arguments are from 0 to 7. 143 $ref: /schemas/types.yaml#/definitions/uint32 144 enum: [0, 1, 2, 3, 4, 5, 6, 7] 145 146 mediatek,pull-up-adv: 147 description: | 148 Pull up settings for 2 pull resistors, R0 and R1. User can 149 configure those special pins. Valid arguments are described as 150 below: 151 0: (R1, R0) = (0, 0) which means R1 disabled and R0 disabled. 152 1: (R1, R0) = (0, 1) which means R1 disabled and R0 enabled. 153 2: (R1, R0) = (1, 0) which means R1 enabled and R0 disabled. 154 3: (R1, R0) = (1, 1) which means R1 enabled and R0 enabled. 155 $ref: /schemas/types.yaml#/definitions/uint32 156 enum: [0, 1, 2, 3] 157 158 mediatek,pull-down-adv: 159 description: | 160 Pull down settings for 2 pull resistors, R0 and R1. User can 161 configure those special pins. Valid arguments are described as 162 below: 163 0: (R1, R0) = (0, 0) which means R1 disabled and R0 disabled. 164 1: (R1, R0) = (0, 1) which means R1 disabled and R0 enabled. 165 2: (R1, R0) = (1, 0) which means R1 enabled and R0 disabled. 166 3: (R1, R0) = (1, 1) which means R1 enabled and R0 enabled. 167 $ref: /schemas/types.yaml#/definitions/uint32 168 enum: [0, 1, 2, 3] 169 170 mediatek,tdsel: 171 description: 172 An integer describing the steps for output level shifter duty 173 cycle when asserted (high pulse width adjustment). Valid arguments 174 are from 0 to 15. 175 $ref: /schemas/types.yaml#/definitions/uint32 176 177 mediatek,rdsel: 178 description: 179 An integer describing the steps for input level shifter duty cycle 180 when asserted (high pulse width adjustment). Valid arguments are 181 from 0 to 63. 182 $ref: /schemas/types.yaml#/definitions/uint32 183 184 required: 185 - pinmux 186 187additionalProperties: false 188 189examples: 190 - | 191 #include <dt-bindings/interrupt-controller/irq.h> 192 #include <dt-bindings/interrupt-controller/arm-gic.h> 193 #include <dt-bindings/pinctrl/mt8183-pinfunc.h> 194 195 soc { 196 #address-cells = <2>; 197 #size-cells = <2>; 198 199 pio: pinctrl@10005000 { 200 compatible = "mediatek,mt8183-pinctrl"; 201 reg = <0 0x10005000 0 0x1000>, 202 <0 0x11f20000 0 0x1000>, 203 <0 0x11e80000 0 0x1000>, 204 <0 0x11e70000 0 0x1000>, 205 <0 0x11e90000 0 0x1000>, 206 <0 0x11d30000 0 0x1000>, 207 <0 0x11d20000 0 0x1000>, 208 <0 0x11c50000 0 0x1000>, 209 <0 0x11f30000 0 0x1000>, 210 <0 0x1000b000 0 0x1000>; 211 reg-names = "iocfg0", "iocfg1", "iocfg2", 212 "iocfg3", "iocfg4", "iocfg5", 213 "iocfg6", "iocfg7", "iocfg8", 214 "eint"; 215 gpio-controller; 216 #gpio-cells = <2>; 217 gpio-ranges = <&pio 0 0 192>; 218 interrupt-controller; 219 interrupts = <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>; 220 #interrupt-cells = <2>; 221 222 i2c0_pins_a: i2c0-pins { 223 pins1 { 224 pinmux = <PINMUX_GPIO48__FUNC_SCL5>, 225 <PINMUX_GPIO49__FUNC_SDA5>; 226 mediatek,pull-up-adv = <3>; 227 drive-strength-microamp = <1000>; 228 }; 229 }; 230 231 i2c1_pins_a: i2c1-pins { 232 pins { 233 pinmux = <PINMUX_GPIO50__FUNC_SCL3>, 234 <PINMUX_GPIO51__FUNC_SDA3>; 235 mediatek,pull-down-adv = <2>; 236 }; 237 }; 238 }; 239 }; 240