1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2%YAML 1.2 3--- 4$id: http://devicetree.org/schemas/pinctrl/mediatek,mt6878-pinctrl.yaml# 5$schema: http://devicetree.org/meta-schemas/core.yaml# 6 7title: MediaTek MT6878 Pin Controller 8 9maintainers: 10 - AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> 11 - Igor Belwon <igor.belwon@mentallysanemainliners.org> 12 13description: 14 The MediaTek MT6878 Pin controller is used to control SoC pins. 15 16properties: 17 compatible: 18 const: mediatek,mt6878-pinctrl 19 20 reg: 21 items: 22 - description: pin controller base 23 - description: bl group IO 24 - description: bm group IO 25 - description: br group IO 26 - description: bl1 group IO 27 - description: br1 group IO 28 - description: lm group IO 29 - description: lt group IO 30 - description: rm group IO 31 - description: rt group IO 32 - description: EINT controller E block 33 - description: EINT controller S block 34 - description: EINT controller W block 35 - description: EINT controller C block 36 37 reg-names: 38 items: 39 - const: base 40 - const: bl 41 - const: bm 42 - const: br 43 - const: bl1 44 - const: br1 45 - const: lm 46 - const: lt 47 - const: rm 48 - const: rt 49 - const: eint-e 50 - const: eint-s 51 - const: eint-w 52 - const: eint-c 53 54 gpio-controller: true 55 56 '#gpio-cells': 57 description: 58 Number of cells in GPIO specifier. Since the generic GPIO binding is used, 59 the amount of cells must be specified as 2. See the below mentioned gpio 60 binding representation for description of particular cells. 61 const: 2 62 63 gpio-ranges: 64 maxItems: 1 65 66 gpio-line-names: 67 maxItems: 216 68 69 interrupts: 70 description: The interrupt outputs to sysirq 71 maxItems: 1 72 73 interrupt-controller: true 74 75 '#interrupt-cells': 76 const: 2 77 78# PIN CONFIGURATION NODES 79patternProperties: 80 '-pins$': 81 type: object 82 additionalProperties: false 83 84 patternProperties: 85 '^pins': 86 type: object 87 allOf: 88 - $ref: /schemas/pinctrl/pincfg-node.yaml 89 - $ref: /schemas/pinctrl/pinmux-node.yaml 90 description: 91 A pinctrl node should contain at least one subnodes representing the 92 pinctrl groups available on the machine. Each subnode will list the 93 pins it needs, and how they should be configured, with regard to muxer 94 configuration, pullups, drive strength, input enable/disable and input 95 schmitt. 96 97 properties: 98 pinmux: 99 description: 100 Integer array, represents gpio pin number and mux setting. 101 Supported pin number and mux are defined as macros in 102 arch/arm64/boot/dts/mediatek/mt8196-pinfunc.h for this SoC. 103 104 drive-strength: 105 enum: [2, 4, 6, 8, 10, 12, 14, 16] 106 107 drive-strength-microamp: 108 enum: [125, 250, 500, 1000] 109 110 bias-pull-down: 111 oneOf: 112 - type: boolean 113 - enum: [75000, 5000] 114 description: Pull down RSEL type resistance values (in ohms) 115 description: 116 For normal pull down type there is no need to specify a resistance 117 value, hence this can be specified as a boolean property. 118 For RSEL pull down type a resistance value (in ohms) can be added. 119 120 bias-pull-up: 121 oneOf: 122 - type: boolean 123 - enum: [10000, 5000, 4000, 3000] 124 description: Pull up RSEL type resistance values (in ohms) 125 description: 126 For normal pull up type there is no need to specify a resistance 127 value, hence this can be specified as a boolean property. 128 For RSEL pull up type a resistance value (in ohms) can be added. 129 130 bias-disable: true 131 132 output-high: true 133 134 output-low: true 135 136 input-enable: true 137 138 input-disable: true 139 140 input-schmitt-enable: true 141 142 input-schmitt-disable: true 143 144 required: 145 - pinmux 146 147 additionalProperties: false 148 149required: 150 - compatible 151 - reg 152 - interrupts 153 - interrupt-controller 154 - '#interrupt-cells' 155 - gpio-controller 156 - '#gpio-cells' 157 - gpio-ranges 158 159additionalProperties: false 160 161examples: 162 - | 163 #include <dt-bindings/interrupt-controller/arm-gic.h> 164 #include <dt-bindings/pinctrl/mt65xx.h> 165 #define PINMUX_GPIO0__FUNC_GPIO0 (MTK_PIN_NO(0) | 0) 166 #define PINMUX_GPIO99__FUNC_SCL0 (MTK_PIN_NO(99) | 1) 167 #define PINMUX_GPIO100__FUNC_SDA0 (MTK_PIN_NO(100) | 1) 168 169 pio: pinctrl@10005000 { 170 compatible = "mediatek,mt6878-pinctrl"; 171 reg = <0x10005000 0x1000>, 172 <0x11d10000 0x1000>, 173 <0x11d30000 0x1000>, 174 <0x11d40000 0x1000>, 175 <0x11d50000 0x1000>, 176 <0x11d60000 0x1000>, 177 <0x11e20000 0x1000>, 178 <0x11e30000 0x1000>, 179 <0x11eb0000 0x1000>, 180 <0x11ec0000 0x1000>, 181 <0x11ce0000 0x1000>, 182 <0x11de0000 0x1000>, 183 <0x11e60000 0x1000>, 184 <0x1c01e000 0x1000>; 185 reg-names = "base", "bl", "bm", "br", "bl1", "br1", 186 "lm", "lt", "rm", "rt", "eint-e", "eint-s", 187 "eint-w", "eint-c"; 188 gpio-controller; 189 #gpio-cells = <2>; 190 gpio-ranges = <&pio 0 0 220>; 191 interrupt-controller; 192 interrupts = <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH 0>; 193 #interrupt-cells = <2>; 194 195 gpio-pins { 196 pins { 197 pinmux = <PINMUX_GPIO0__FUNC_GPIO0>; 198 bias-pull-up = <4000>; 199 drive-strength = <6>; 200 }; 201 }; 202 203 i2c0-pins { 204 pins-bus { 205 pinmux = <PINMUX_GPIO99__FUNC_SCL0>, 206 <PINMUX_GPIO100__FUNC_SDA0>; 207 bias-pull-down = <75000>; 208 drive-strength-microamp = <1000>; 209 }; 210 }; 211 }; 212