1# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause 2%YAML 1.2 3--- 4$id: http://devicetree.org/schemas/pinctrl/fsl,imx35-pinctrl.yaml# 5$schema: http://devicetree.org/meta-schemas/core.yaml# 6 7title: Freescale IMX35/IMX5x/IMX6 IOMUX Controller 8 9maintainers: 10 - Dong Aisheng <aisheng.dong@nxp.com> 11 12description: 13 Please refer to fsl,imx-pinctrl.txt and pinctrl-bindings.txt in this directory 14 for common binding part and usage. 15 16allOf: 17 - $ref: pinctrl.yaml# 18 19properties: 20 compatible: 21 oneOf: 22 - enum: 23 - fsl,imx25-iomuxc 24 - fsl,imx35-iomuxc 25 - fsl,imx51-iomuxc 26 - fsl,imx53-iomuxc 27 - fsl,imx6dl-iomuxc 28 - fsl,imx6q-iomuxc 29 - fsl,imx6sl-iomuxc 30 - fsl,imx6sll-iomuxc 31 - fsl,imx6sx-iomuxc 32 - fsl,imx6ul-iomuxc 33 - fsl,imx6ull-iomuxc-snvs 34 - items: 35 - const: fsl,imx50-iomuxc 36 - const: fsl,imx53-iomuxc 37 38 reg: 39 maxItems: 1 40 41# Client device subnode's properties 42patternProperties: 43 'grp$': 44 type: object 45 description: 46 Pinctrl node's client devices use subnodes for desired pin configuration. 47 Client device subnodes use below standard properties. 48 49 properties: 50 fsl,pins: 51 description: 52 each entry consists of 6 integers and represents the mux and config 53 setting for one pin. The first 5 integers <mux_reg conf_reg input_reg 54 mux_val input_val> are specified using a PIN_FUNC_ID macro, which can 55 be found in <arch/arm/boot/dts/nxp/imx/imx*-pinfunc.h>. The last integer 56 CONFIG is the pad setting value like pull-up on this pin. Please 57 refer to matching i.MX Reference Manual for detailed CONFIG settings. 58 $ref: /schemas/types.yaml#/definitions/uint32-matrix 59 items: 60 items: 61 - description: | 62 "mux_reg" indicates the offset of mux register. 63 - description: | 64 "conf_reg" indicates the offset of pad configuration register. 65 - description: | 66 "input_reg" indicates the offset of select input register. 67 - description: | 68 "mux_val" indicates the mux value to be applied. 69 - description: | 70 "input_val" indicates the select input value to be applied. 71 - description: | 72 "pad_setting" indicates the pad configuration value to be applied. 73 Common i.MX35 74 PAD_CTL_DRIVE_VOLAGAGE_18 (1 << 13) 75 PAD_CTL_DRIVE_VOLAGAGE_33 (0 << 13) 76 PAD_CTL_HYS (1 << 8) 77 PAD_CTL_PKE (1 << 7) 78 PAD_CTL_PUE (1 << 6) 79 PAD_CTL_PUS_100K_DOWN (0 << 4) 80 PAD_CTL_PUS_47K_UP (1 << 4) 81 PAD_CTL_PUS_100K_UP (2 << 4) 82 PAD_CTL_PUS_22K_UP (3 << 4) 83 PAD_CTL_ODE_CMOS (0 << 3) 84 PAD_CTL_ODE_OPENDRAIN (1 << 3) 85 PAD_CTL_DSE_NOMINAL (0 << 1) 86 PAD_CTL_DSE_HIGH (1 << 1) 87 PAD_CTL_DSE_MAX (2 << 1) 88 PAD_CTL_SRE_FAST (1 << 0) 89 PAD_CTL_SRE_SLOW (0 << 0) 90 Common i.MX50/i.MX51/i.MX53 bits 91 PAD_CTL_HVE (1 << 13) 92 PAD_CTL_HYS (1 << 8) 93 PAD_CTL_PKE (1 << 7) 94 PAD_CTL_PUE (1 << 6) 95 PAD_CTL_PUS_100K_DOWN (0 << 4) 96 PAD_CTL_PUS_47K_UP (1 << 4) 97 PAD_CTL_PUS_100K_UP (2 << 4) 98 PAD_CTL_PUS_22K_UP (3 << 4) 99 PAD_CTL_ODE (1 << 3) 100 PAD_CTL_DSE_LOW (0 << 1) 101 PAD_CTL_DSE_MED (1 << 1) 102 PAD_CTL_DSE_HIGH (2 << 1) 103 PAD_CTL_DSE_MAX (3 << 1) 104 PAD_CTL_SRE_FAST (1 << 0) 105 PAD_CTL_SRE_SLOW (0 << 0) 106 Common i.MX6 bits 107 PAD_CTL_HYS (1 << 16) 108 PAD_CTL_PUS_100K_DOWN (0 << 14) 109 PAD_CTL_PUS_47K_UP (1 << 14) 110 PAD_CTL_PUS_100K_UP (2 << 14) 111 PAD_CTL_PUS_22K_UP (3 << 14) 112 PAD_CTL_PUE (1 << 13) 113 PAD_CTL_PKE (1 << 12) 114 PAD_CTL_ODE (1 << 11) 115 PAD_CTL_SPEED_LOW (0 << 6) 116 PAD_CTL_SPEED_MED (1 << 6) 117 PAD_CTL_SPEED_HIGH (3 << 6) 118 PAD_CTL_DSE_DISABLE (0 << 3) 119 PAD_CTL_SRE_FAST (1 << 0) 120 PAD_CTL_SRE_SLOW (0 << 0) 121 i.MX6SL/MX6SLL specific bits 122 PAD_CTL_LVE (1 << 22) (MX6SL/SLL only) 123 i.MX6SLL/i.MX6SX/i.MX6UL/i.MX6ULL specific bits 124 PAD_CTL_DSE_260ohm (1 << 3) 125 PAD_CTL_DSE_130ohm (2 << 3) 126 PAD_CTL_DSE_87ohm (3 << 3) 127 PAD_CTL_DSE_65ohm (4 << 3) 128 PAD_CTL_DSE_52ohm (5 << 3) 129 PAD_CTL_DSE_43ohm (6 << 3) 130 PAD_CTL_DSE_37ohm (7 << 3) 131 i.MX6DL/i.MX6Q/i.MX6SL specific bits 132 PAD_CTL_DSE_240ohm (1 << 3) 133 PAD_CTL_DSE_120ohm (2 << 3) 134 PAD_CTL_DSE_80ohm (3 << 3) 135 PAD_CTL_DSE_60ohm (4 << 3) 136 PAD_CTL_DSE_48ohm (5 << 3) 137 PAD_CTL_DSE_40ohm (6 << 3) 138 PAD_CTL_DSE_34ohm (7 << 3) 139 140 required: 141 - fsl,pins 142 143 additionalProperties: false 144 145required: 146 - compatible 147 - reg 148 149additionalProperties: false 150 151examples: 152 - | 153 iomuxc: pinctrl@20e0000 { 154 compatible = "fsl,imx6ul-iomuxc"; 155 reg = <0x020e0000 0x4000>; 156 157 mux_uart: uartgrp { 158 fsl,pins = < 159 0x0084 0x0310 0x0000 0 0 0x1b0b1 160 0x0088 0x0314 0x0624 0 3 0x1b0b1 161 >; 162 }; 163 }; 164 - | 165 iomuxc_snvs: pinctrl@2290000 { 166 compatible = "fsl,imx6ull-iomuxc-snvs"; 167 reg = <0x02290000 0x4000>; 168 169 pinctrl_snvs_usbc_det: snvsusbcdetgrp { 170 fsl,pins = < 171 0x0010 0x0054 0x0000 0x5 0x0 0x130b0 172 >; 173 }; 174 }; 175 - | 176 iomuxc_mx6q: pinctrl@20e0000 { 177 compatible = "fsl,imx6q-iomuxc"; 178 reg = <0x20e0000 0x4000>; 179 180 pinctrl_uart4: uart4grp { 181 fsl,pins = 182 <0x288 0x658 0x000 0x3 0x0 0x140>, 183 <0x28c 0x65c 0x938 0x3 0x3 0x140>; 184 }; 185 }; 186