1# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause 2%YAML 1.2 3--- 4$id: http://devicetree.org/schemas/pinctrl/fsl,imx9-pinctrl.yaml# 5$schema: http://devicetree.org/meta-schemas/core.yaml# 6 7title: Freescale IMX9 IOMUX Controller 8 9maintainers: 10 - Peng Fan <peng.fan@nxp.com> 11 12description: 13 Please refer to fsl,imx-pinctrl.txt and pinctrl-bindings.txt in this directory 14 for common binding part and usage. 15 16allOf: 17 - $ref: pinctrl.yaml# 18 19properties: 20 compatible: 21 enum: 22 - fsl,imx91-iomuxc 23 - fsl,imx93-iomuxc 24 25 reg: 26 maxItems: 1 27 28# Client device subnode's properties 29patternProperties: 30 'grp$': 31 type: object 32 description: 33 Pinctrl node's client devices use subnodes for desired pin configuration. 34 Client device subnodes use below standard properties. 35 36 properties: 37 fsl,pins: 38 description: 39 each entry consists of 6 integers and represents the mux and config 40 setting for one pin. The first 5 integers <mux_reg conf_reg input_reg 41 mux_val input_val> are specified using a PIN_FUNC_ID macro, which can 42 be found in <arch/arm64/boot/dts/freescale/imx8mp-pinfunc.h>. The last 43 integer CONFIG is the pad setting value like pull-up on this pin. Please 44 refer to i.MX8M Plus Reference Manual for detailed CONFIG settings. 45 $ref: /schemas/types.yaml#/definitions/uint32-matrix 46 items: 47 items: 48 - description: | 49 "mux_reg" indicates the offset of mux register. 50 - description: | 51 "conf_reg" indicates the offset of pad configuration register. 52 - description: | 53 "input_reg" indicates the offset of select input register. 54 - description: | 55 "mux_val" indicates the mux value to be applied. 56 - description: | 57 "input_val" indicates the select input value to be applied. 58 - description: | 59 "pad_setting" indicates the pad configuration value to be applied. 60 61 62 required: 63 - fsl,pins 64 65 additionalProperties: false 66 67required: 68 - compatible 69 - reg 70 71additionalProperties: false 72 73examples: 74 # Pinmux controller node 75 - | 76 iomuxc: pinctrl@443c0000 { 77 compatible = "fsl,imx93-iomuxc"; 78 reg = <0x30330000 0x10000>; 79 80 pinctrl_uart3: uart3grp { 81 fsl,pins = 82 <0x48 0x1f8 0x41c 0x1 0x0 0x49>, 83 <0x4c 0x1fc 0x418 0x1 0x0 0x49>; 84 }; 85 }; 86 87... 88