1TI PHY: DT DOCUMENTATION FOR PHYs in TI PLATFORMs 2 3OMAP CONTROL PHY 4 5Required properties: 6 - compatible: Should be one of 7 "ti,control-phy-otghs" - if it has otghs_control mailbox register as on OMAP4. 8 "ti,control-phy-usb2" - if it has Power down bit in control_dev_conf register 9 e.g. USB2_PHY on OMAP5. 10 "ti,control-phy-pipe3" - if it has DPLL and individual Rx & Tx power control 11 e.g. USB3 PHY and SATA PHY on OMAP5. 12 "ti,control-phy-pcie" - for pcie to support external clock for pcie and to 13 set PCS delay value. 14 e.g. PCIE PHY in DRA7x 15 "ti,control-phy-usb2-dra7" - if it has power down register like USB2 PHY on 16 DRA7 platform. 17 "ti,control-phy-usb2-am437" - if it has power down register like USB2 PHY on 18 AM437 platform. 19 - reg : register ranges as listed in the reg-names property 20 - reg-names: "otghs_control" for control-phy-otghs 21 "power", "pcie_pcs" and "control_sma" for control-phy-pcie 22 "power" for all other types 23 24omap_control_usb: omap-control-usb@4a002300 { 25 compatible = "ti,control-phy-otghs"; 26 reg = <0x4a00233c 0x4>; 27 reg-names = "otghs_control"; 28}; 29 30OMAP USB2 PHY 31 32Required properties: 33 - compatible: Should be "ti,omap-usb2" 34 - reg : Address and length of the register set for the device. 35 - #phy-cells: determine the number of cells that should be given in the 36 phandle while referencing this phy. 37 - clocks: a list of phandles and clock-specifier pairs, one for each entry in 38 clock-names. 39 - clock-names: should include: 40 * "wkupclk" - wakeup clock. 41 * "refclk" - reference clock (optional). 42 43Optional properties: 44 - ctrl-module : phandle of the control module used by PHY driver to power on 45 the PHY. 46 47This is usually a subnode of ocp2scp to which it is connected. 48 49usb2phy@4a0ad080 { 50 compatible = "ti,omap-usb2"; 51 reg = <0x4a0ad080 0x58>; 52 ctrl-module = <&omap_control_usb>; 53 #phy-cells = <0>; 54 clocks = <&usb_phy_cm_clk32k>, <&usb_otg_ss_refclk960m>; 55 clock-names = "wkupclk", "refclk"; 56}; 57 58TI PIPE3 PHY 59 60Required properties: 61 - compatible: Should be "ti,phy-usb3", "ti,phy-pipe3-sata" or 62 "ti,phy-pipe3-pcie. "ti,omap-usb3" is deprecated. 63 - reg : Address and length of the register set for the device. 64 - reg-names: The names of the register addresses corresponding to the registers 65 filled in "reg". 66 - #phy-cells: determine the number of cells that should be given in the 67 phandle while referencing this phy. 68 - clocks: a list of phandles and clock-specifier pairs, one for each entry in 69 clock-names. 70 - clock-names: should include: 71 * "wkupclk" - wakeup clock. 72 * "sysclk" - system clock. 73 * "refclk" - reference clock. 74 * "dpll_ref" - external dpll ref clk 75 * "dpll_ref_m2" - external dpll ref clk 76 * "phy-div" - divider for apll 77 * "div-clk" - apll clock 78 79Optional properties: 80 - ctrl-module : phandle of the control module used by PHY driver to power on 81 the PHY. 82 - id: If there are multiple instance of the same type, in order to 83 differentiate between each instance "id" can be used (e.g., multi-lane PCIe 84 PHY). If "id" is not provided, it is set to default value of '1'. 85 - syscon-pllreset: Handle to system control region that contains the 86 CTRL_CORE_SMA_SW_0 register and register offset to the CTRL_CORE_SMA_SW_0 87 register that contains the SATA_PLL_SOFT_RESET bit. Only valid for sata_phy. 88 89This is usually a subnode of ocp2scp to which it is connected. 90 91usb3phy@4a084400 { 92 compatible = "ti,phy-usb3"; 93 reg = <0x4a084400 0x80>, 94 <0x4a084800 0x64>, 95 <0x4a084c00 0x40>; 96 reg-names = "phy_rx", "phy_tx", "pll_ctrl"; 97 ctrl-module = <&omap_control_usb>; 98 #phy-cells = <0>; 99 clocks = <&usb_phy_cm_clk32k>, 100 <&sys_clkin>, 101 <&usb_otg_ss_refclk960m>; 102 clock-names = "wkupclk", 103 "sysclk", 104 "refclk"; 105}; 106 107sata_phy: phy@4A096000 { 108 compatible = "ti,phy-pipe3-sata"; 109 reg = <0x4A096000 0x80>, /* phy_rx */ 110 <0x4A096400 0x64>, /* phy_tx */ 111 <0x4A096800 0x40>; /* pll_ctrl */ 112 reg-names = "phy_rx", "phy_tx", "pll_ctrl"; 113 ctrl-module = <&omap_control_sata>; 114 clocks = <&sys_clkin1>, <&sata_ref_clk>; 115 clock-names = "sysclk", "refclk"; 116 syscon-pllreset = <&scm_conf 0x3fc>; 117 #phy-cells = <0>; 118}; 119