xref: /linux/Documentation/devicetree/bindings/phy/ti,phy-usb3.yaml (revision 1fd1dc41724319406b0aff221a352a400b0ddfc5) 
1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/phy/ti,phy-usb3.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: TI PIPE3 PHY Module
8
9maintainers:
10  - Roger Quadros <rogerq@ti.com>
11
12description:
13  The TI PIPE3 PHY is a high-speed SerDes (Serializer/Deserializer)
14  transceiver integrated in OMAP5, DRA7xx/AM57xx, and similar SoCs.
15  It supports multiple protocols (USB3, SATA, PCIe) using the PIPE3
16  interface standard, which defines a common physical layer for
17  high-speed serial interfaces.
18
19properties:
20  $nodename:
21    pattern: "^(pcie-phy|usb3-phy|phy)@[0-9a-f]+$"
22
23  compatible:
24    enum:
25      - ti,omap-usb3
26      - ti,phy-pipe3-pcie
27      - ti,phy-pipe3-sata
28      - ti,phy-usb3
29
30  reg:
31    minItems: 2
32    maxItems: 3
33
34  reg-names:
35    minItems: 2
36    items:
37      - const: phy_rx
38      - const: phy_tx
39      - const: pll_ctrl
40
41  "#phy-cells":
42    const: 0
43
44  clocks:
45    minItems: 2
46    maxItems: 7
47
48  clock-names:
49    minItems: 2
50    maxItems: 7
51    items:
52      enum: [wkupclk, sysclk, refclk, dpll_ref,
53             dpll_ref_m2, phy-div, div-clk]
54
55  syscon-phy-power:
56    $ref: /schemas/types.yaml#/definitions/phandle-array
57    maxItems: 1
58    items:
59      items:
60        - description: Phandle to the system control module
61        - description: Register offset controlling PHY power
62
63  syscon-pllreset:
64    $ref: /schemas/types.yaml#/definitions/phandle-array
65    maxItems: 1
66    items:
67      items:
68        - description: Phandle to the system control module
69        - description: Register offset of CTRL_CORE_SMA_SW_0
70
71  syscon-pcs:
72    $ref: /schemas/types.yaml#/definitions/phandle-array
73    maxItems: 1
74    items:
75      items:
76        - description: Phandle to the system control module
77        - description: Register offset for PCS delay programming
78
79  ctrl-module:
80    $ref: /schemas/types.yaml#/definitions/phandle
81    description:
82      Phandle of control module for PHY power on.
83    deprecated: true
84
85allOf:
86  - if:
87      properties:
88        compatible:
89          contains:
90            const: ti,phy-pipe3-sata
91    then:
92      properties:
93        syscon-pllreset: true
94    else:
95      properties:
96        syscon-pllreset: false
97
98required:
99  - reg
100  - compatible
101  - reg-names
102  - "#phy-cells"
103  - clocks
104  - clock-names
105
106unevaluatedProperties: false
107
108examples:
109  - |
110    /* TI PIPE3 USB3 PHY */
111    usb3-phy@4a084400 {
112        compatible = "ti,phy-usb3";
113        reg = <0x4a084400 0x80>,
114              <0x4a084800 0x64>,
115              <0x4a084c00 0x40>;
116        reg-names = "phy_rx", "phy_tx", "pll_ctrl";
117        #phy-cells = <0>;
118        clocks = <&usb_phy_cm_clk32k>,
119                 <&sys_clkin>,
120                 <&usb_otg_ss_refclk960m>;
121        clock-names = "wkupclk", "sysclk", "refclk";
122        ctrl-module = <&omap_control_usb>;
123    };
124
125  - |
126    /* TI PIPE3 SATA PHY */
127    phy@4a096000 {
128        compatible = "ti,phy-pipe3-sata";
129        reg = <0x4a096000 0x80>,  /* phy_rx */
130              <0x4a096400 0x64>,  /* phy_tx */
131              <0x4a096800 0x40>;  /* pll_ctrl */
132        reg-names = "phy_rx", "phy_tx", "pll_ctrl";
133        clocks = <&sys_clkin1>, <&sata_ref_clk>;
134        clock-names = "sysclk", "refclk";
135        syscon-pllreset = <&scm_conf 0x3fc>;
136        #phy-cells = <0>;
137    };
138...
139