1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2# Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com/ 3%YAML 1.2 4--- 5$id: "http://devicetree.org/schemas/phy/ti,phy-j721e-wiz.yaml#" 6$schema: "http://devicetree.org/meta-schemas/core.yaml#" 7 8title: TI J721E WIZ (SERDES Wrapper) 9 10maintainers: 11 - Kishon Vijay Abraham I <kishon@ti.com> 12 13properties: 14 compatible: 15 enum: 16 - ti,j721e-wiz-16g 17 - ti,j721e-wiz-10g 18 19 power-domains: 20 maxItems: 1 21 22 clocks: 23 maxItems: 3 24 description: clock-specifier to represent input to the WIZ 25 26 clock-names: 27 items: 28 - const: fck 29 - const: core_ref_clk 30 - const: ext_ref_clk 31 32 num-lanes: 33 minimum: 1 34 maximum: 4 35 36 "#address-cells": 37 const: 1 38 39 "#size-cells": 40 const: 1 41 42 "#reset-cells": 43 const: 1 44 45 ranges: true 46 47 assigned-clocks: 48 maxItems: 2 49 50 assigned-clock-parents: 51 maxItems: 2 52 53 typec-dir-gpios: 54 maxItems: 1 55 description: 56 GPIO to signal Type-C cable orientation for lane swap. 57 If GPIO is active, lane 0 and lane 1 of SERDES will be swapped to 58 achieve the funtionality of an external type-C plug flip mux. 59 60 typec-dir-debounce-ms: 61 minimum: 100 62 maximum: 1000 63 default: 100 64 description: 65 Number of milliseconds to wait before sampling typec-dir-gpio. 66 If not specified, the default debounce of 100ms will be used. 67 Type-C spec states minimum CC pin debounce of 100 ms and maximum 68 of 200 ms. However, some solutions might need more than 200 ms. 69 70patternProperties: 71 "^pll[0|1]-refclk$": 72 type: object 73 description: | 74 WIZ node should have subnodes for each of the PLLs present in 75 the SERDES. 76 properties: 77 clocks: 78 maxItems: 2 79 description: Phandle to clock nodes representing the two inputs to PLL. 80 81 "#clock-cells": 82 const: 0 83 84 assigned-clocks: 85 maxItems: 1 86 87 assigned-clock-parents: 88 maxItems: 1 89 90 required: 91 - clocks 92 - "#clock-cells" 93 - assigned-clocks 94 - assigned-clock-parents 95 96 "^cmn-refclk1?-dig-div$": 97 type: object 98 description: 99 WIZ node should have subnodes for each of the PMA common refclock 100 provided by the SERDES. 101 properties: 102 clocks: 103 maxItems: 1 104 description: Phandle to the clock node representing the input to the 105 divider clock. 106 107 "#clock-cells": 108 const: 0 109 110 required: 111 - clocks 112 - "#clock-cells" 113 114 "^refclk-dig$": 115 type: object 116 description: | 117 WIZ node should have subnode for refclk_dig to select the reference 118 clock source for the reference clock used in the PHY and PMA digital 119 logic. 120 properties: 121 clocks: 122 maxItems: 4 123 description: Phandle to four clock nodes representing the inputs to 124 refclk_dig 125 126 "#clock-cells": 127 const: 0 128 129 assigned-clocks: 130 maxItems: 1 131 132 assigned-clock-parents: 133 maxItems: 1 134 135 required: 136 - clocks 137 - "#clock-cells" 138 - assigned-clocks 139 - assigned-clock-parents 140 141 "^serdes@[0-9a-f]+$": 142 type: object 143 description: | 144 WIZ node should have '1' subnode for the SERDES. It could be either 145 Sierra SERDES or Torrent SERDES. Sierra SERDES should follow the 146 bindings specified in 147 Documentation/devicetree/bindings/phy/phy-cadence-sierra.txt 148 Torrent SERDES should follow the bindings specified in 149 Documentation/devicetree/bindings/phy/phy-cadence-torrent.yaml 150 151required: 152 - compatible 153 - power-domains 154 - clocks 155 - clock-names 156 - num-lanes 157 - "#address-cells" 158 - "#size-cells" 159 - "#reset-cells" 160 - ranges 161 162additionalProperties: false 163 164examples: 165 - | 166 #include <dt-bindings/soc/ti,sci_pm_domain.h> 167 168 wiz@5000000 { 169 compatible = "ti,j721e-wiz-16g"; 170 #address-cells = <1>; 171 #size-cells = <1>; 172 power-domains = <&k3_pds 292 TI_SCI_PD_EXCLUSIVE>; 173 clocks = <&k3_clks 292 5>, <&k3_clks 292 11>, <&dummy_cmn_refclk>; 174 clock-names = "fck", "core_ref_clk", "ext_ref_clk"; 175 assigned-clocks = <&k3_clks 292 11>, <&k3_clks 292 0>; 176 assigned-clock-parents = <&k3_clks 292 15>, <&k3_clks 292 4>; 177 num-lanes = <2>; 178 #reset-cells = <1>; 179 ranges = <0x5000000 0x5000000 0x10000>; 180 181 pll0-refclk { 182 clocks = <&k3_clks 293 13>, <&dummy_cmn_refclk>; 183 #clock-cells = <0>; 184 assigned-clocks = <&wiz1_pll0_refclk>; 185 assigned-clock-parents = <&k3_clks 293 13>; 186 }; 187 188 pll1-refclk { 189 clocks = <&k3_clks 293 0>, <&dummy_cmn_refclk1>; 190 #clock-cells = <0>; 191 assigned-clocks = <&wiz1_pll1_refclk>; 192 assigned-clock-parents = <&k3_clks 293 0>; 193 }; 194 195 cmn-refclk-dig-div { 196 clocks = <&wiz1_refclk_dig>; 197 #clock-cells = <0>; 198 }; 199 200 cmn-refclk1-dig-div { 201 clocks = <&wiz1_pll1_refclk>; 202 #clock-cells = <0>; 203 }; 204 205 refclk-dig { 206 clocks = <&k3_clks 292 11>, <&k3_clks 292 0>, <&dummy_cmn_refclk>, <&dummy_cmn_refclk1>; 207 #clock-cells = <0>; 208 assigned-clocks = <&wiz0_refclk_dig>; 209 assigned-clock-parents = <&k3_clks 292 11>; 210 }; 211 212 serdes@5000000 { 213 compatible = "cdns,ti,sierra-phy-t0"; 214 reg-names = "serdes"; 215 reg = <0x5000000 0x10000>; 216 #address-cells = <1>; 217 #size-cells = <0>; 218 resets = <&serdes_wiz0 0>; 219 reset-names = "sierra_reset"; 220 clocks = <&wiz0_cmn_refclk_dig_div>, <&wiz0_cmn_refclk1_dig_div>; 221 clock-names = "cmn_refclk_dig_div", "cmn_refclk1_dig_div"; 222 }; 223 }; 224