xref: /linux/Documentation/devicetree/bindings/phy/ti,phy-gmii-sel.yaml (revision 9f2c9170934eace462499ba0bfe042cc72900173) 
1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2# Copyright (C) 2020 Texas Instruments Incorporated - http://www.ti.com/
3%YAML 1.2
4---
5$id: "http://devicetree.org/schemas/phy/ti,phy-gmii-sel.yaml#"
6$schema: "http://devicetree.org/meta-schemas/core.yaml#"
7
8title: CPSW Port's Interface Mode Selection PHY
9
10maintainers:
11  - Kishon Vijay Abraham I <kishon@ti.com>
12
13description: |
14  TI am335x/am437x/dra7(am5)/dm814x CPSW3G Ethernet Subsystem supports
15  two 10/100/1000 Ethernet ports with selectable G/MII, RMII, and RGMII interfaces.
16  The interface mode is selected by configuring the MII mode selection register(s)
17  (GMII_SEL) in the System Control Module chapter (SCM). GMII_SEL register(s) and
18  bit fields placement in SCM are different between SoCs while fields meaning
19  is the same.
20                                               +--------------+
21        +-------------------------------+      |SCM           |
22        |                     CPSW      |      |  +---------+ |
23        |        +--------------------------------+gmii_sel | |
24        |        |                      |      |  +---------+ |
25        |   +----v---+     +--------+   |      +--------------+
26        |   |Port 1..<--+-->GMII/MII<------->
27        |   |        |  |  |        |   |
28        |   +--------+  |  +--------+   |
29        |               |               |
30        |               |  +--------+   |
31        |               |  | RMII   <------->
32        |               +-->        |   |
33        |               |  +--------+   |
34        |               |               |
35        |               |  +--------+   |
36        |               |  | RGMII  <------->
37        |               +-->        |   |
38        |                  +--------+   |
39        +-------------------------------+
40
41  CPSW Port's Interface Mode Selection PHY describes MII interface mode between
42  CPSW Port and Ethernet PHY which depends on Eth PHY and board configuration.
43  |
44  CPSW Port's Interface Mode Selection PHY device should defined as child device
45  of SCM node (scm_conf) and can be attached to each CPSW port node using standard
46  PHY bindings.
47
48properties:
49  compatible:
50    enum:
51      - ti,am3352-phy-gmii-sel
52      - ti,dra7xx-phy-gmii-sel
53      - ti,am43xx-phy-gmii-sel
54      - ti,dm814-phy-gmii-sel
55      - ti,am654-phy-gmii-sel
56      - ti,j7200-cpsw5g-phy-gmii-sel
57      - ti,j721e-cpsw9g-phy-gmii-sel
58
59  reg:
60    maxItems: 1
61
62  '#phy-cells': true
63
64  ti,qsgmii-main-ports:
65    $ref: /schemas/types.yaml#/definitions/uint32-array
66    description: |
67      Required only for QSGMII mode. Array to select the port/s for QSGMII
68      main mode. The size of the array corresponds to the number of QSGMII
69      interfaces and thus, the number of distinct QSGMII main ports,
70      supported by the device. If the device supports two QSGMII interfaces
71      but only one QSGMII interface is desired, repeat the QSGMII main port
72      value corresponding to the QSGMII interface in the array.
73    minItems: 1
74    maxItems: 2
75    items:
76      minimum: 1
77      maximum: 8
78
79allOf:
80  - if:
81      properties:
82        compatible:
83          contains:
84            enum:
85              - ti,dra7xx-phy-gmii-sel
86              - ti,dm814-phy-gmii-sel
87              - ti,am654-phy-gmii-sel
88              - ti,j7200-cpsw5g-phy-gmii-sel
89              - ti,j721e-cpsw9g-phy-gmii-sel
90    then:
91      properties:
92        '#phy-cells':
93          const: 1
94          description: CPSW port number (starting from 1)
95
96  - if:
97      properties:
98        compatible:
99          contains:
100            enum:
101              - ti,j7200-cpsw5g-phy-gmii-sel
102    then:
103      properties:
104        ti,qsgmii-main-ports:
105          maxItems: 1
106          items:
107            minimum: 1
108            maximum: 4
109
110  - if:
111      properties:
112        compatible:
113          contains:
114            enum:
115              - ti,j721e-cpsw9g-phy-gmii-sel
116    then:
117      properties:
118        ti,qsgmii-main-ports:
119          minItems: 2
120          maxItems: 2
121          items:
122            minimum: 1
123            maximum: 8
124
125  - if:
126      not:
127        properties:
128          compatible:
129            contains:
130              enum:
131                - ti,j7200-cpsw5g-phy-gmii-sel
132                - ti,j721e-cpsw9g-phy-gmii-sel
133    then:
134      properties:
135        ti,qsgmii-main-ports: false
136
137  - if:
138      properties:
139        compatible:
140          contains:
141            enum:
142              - ti,am3352-phy-gmii-sel
143              - ti,am43xx-phy-gmii-sel
144    then:
145      properties:
146        '#phy-cells':
147          const: 2
148          description: |
149            - CPSW port number (starting from 1)
150            - RMII refclk mode
151
152required:
153  - compatible
154  - reg
155  - '#phy-cells'
156
157additionalProperties: false
158
159examples:
160  - |
161    phy_gmii_sel: phy@650 {
162        compatible = "ti,am3352-phy-gmii-sel";
163        reg = <0x650 0x4>;
164        #phy-cells = <2>;
165    };
166