xref: /linux/Documentation/devicetree/bindings/phy/starfive,jh7110-dphy-tx.yaml (revision a1ff5a7d78a036d6c2178ee5acd6ba4946243800) 
1# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/phy/starfive,jh7110-dphy-tx.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Starfive SoC MIPI D-PHY Tx Controller
8
9maintainers:
10  - Keith Zhao <keith.zhao@starfivetech.com>
11  - Shengyang Chen <shengyang.chen@starfivetech.com>
12
13description:
14  The Starfive SoC uses the MIPI DSI D-PHY based on M31 IP to transfer
15  DSI data.
16
17properties:
18  compatible:
19    const: starfive,jh7110-dphy-tx
20
21  reg:
22    maxItems: 1
23
24  clocks:
25    maxItems: 1
26
27  clock-names:
28    items:
29      - const: txesc
30
31  resets:
32    items:
33      - description: MIPITX_DPHY_SYS reset
34
35  reset-names:
36    items:
37      - const: sys
38
39  power-domains:
40    maxItems: 1
41
42  "#phy-cells":
43    const: 0
44
45required:
46  - compatible
47  - reg
48  - clocks
49  - clock-names
50  - resets
51  - reset-names
52  - power-domains
53  - "#phy-cells"
54
55additionalProperties: false
56
57examples:
58  - |
59    phy@295e0000 {
60      compatible = "starfive,jh7110-dphy-tx";
61      reg = <0x295e0000 0x10000>;
62      clocks = <&voutcrg 14>;
63      clock-names = "txesc";
64      resets = <&syscrg 10>;
65      reset-names = "sys";
66      power-domains = <&aon_syscon 0>;
67      #phy-cells = <0>;
68    };
69