xref: /linux/Documentation/devicetree/bindings/phy/socionext,uniphier-ahci-phy.yaml (revision 34f7c6e7d4396090692a09789db231e12cb4762b) 
1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/phy/socionext,uniphier-ahci-phy.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Socionext UniPhier AHCI PHY
8
9description: |
10  This describes the deivcetree bindings for PHY interfaces built into
11  AHCI controller implemented on Socionext UniPhier SoCs.
12
13maintainers:
14  - Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
15
16properties:
17  compatible:
18    enum:
19      - socionext,uniphier-pro4-ahci-phy
20      - socionext,uniphier-pxs2-ahci-phy
21      - socionext,uniphier-pxs3-ahci-phy
22
23  reg:
24    maxItems: 1
25
26  "#phy-cells":
27    const: 0
28
29  clocks:
30    minItems: 1
31    maxItems: 2
32
33  clock-names:
34    oneOf:
35      - items:          # for PXs2
36          - const: link
37      - items:          # for Pro4
38          - const: link
39          - const: gio
40      - items:          # for others
41          - const: link
42          - const: phy
43
44  resets:
45    minItems: 2
46    maxItems: 5
47
48  reset-names:
49    oneOf:
50      - items:          # for Pro4
51          - const: link
52          - const: gio
53          - const: pm
54          - const: tx
55          - const: rx
56      - items:          # for others
57          - const: link
58          - const: phy
59
60required:
61  - compatible
62  - reg
63  - "#phy-cells"
64  - clocks
65  - clock-names
66  - resets
67  - reset-names
68
69additionalProperties: false
70
71examples:
72  - |
73    ahci-glue@65700000 {
74        compatible = "socionext,uniphier-pxs3-ahci-glue",
75                     "simple-mfd";
76        #address-cells = <1>;
77        #size-cells = <1>;
78        ranges = <0 0x65700000 0x100>;
79
80        ahci_phy: phy@10 {
81            compatible = "socionext,uniphier-pxs3-ahci-phy";
82            reg = <0x10 0x10>;
83            #phy-cells = <0>;
84            clock-names = "link", "phy";
85            clocks = <&sys_clk 28>, <&sys_clk 30>;
86            reset-names = "link", "phy";
87            resets = <&sys_rst 28>, <&sys_rst 30>;
88        };
89    };
90