xref: /linux/Documentation/devicetree/bindings/phy/socionext,uniphier-usb3hs-phy.yaml (revision ceb2465c51195967f11f6507538579816ac67cb8) 
1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/phy/socionext,uniphier-usb3hs-phy.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Socionext UniPhier USB3 High-Speed (HS) PHY
8
9description: |
10  This describes the devicetree bindings for PHY interfaces built into
11  USB3 controller implemented on Socionext UniPhier SoCs.
12  Although the controller includes High-Speed PHY and Super-Speed PHY,
13  this describes about High-Speed PHY.
14
15maintainers:
16  - Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
17
18properties:
19  compatible:
20    enum:
21      - socionext,uniphier-pro5-usb3-hsphy
22      - socionext,uniphier-pxs2-usb3-hsphy
23      - socionext,uniphier-ld20-usb3-hsphy
24      - socionext,uniphier-pxs3-usb3-hsphy
25
26  reg:
27    description: PHY register region (offset and length)
28
29  "#phy-cells":
30    const: 0
31
32  clocks:
33    minItems: 1
34    maxItems: 3
35
36  clock-names:
37    oneOf:
38      - const: link          # for PXs2
39      - items:               # for PXs3 with phy-ext
40          - const: link
41          - const: phy
42          - const: phy-ext
43      - items:               # for others
44          - const: link
45          - const: phy
46
47  resets:
48    maxItems: 2
49
50  reset-names:
51    items:
52      - const: link
53      - const: phy
54
55  vbus-supply:
56    description: A phandle to the regulator for USB VBUS
57
58  nvmem-cells:
59    maxItems: 3
60    description:
61      Phandles to nvmem cell that contains the trimming data.
62      Available only for HS-PHY implemented on LD20 and PXs3, and
63      if unspecified, default value is used.
64
65  nvmem-cell-names:
66    items:
67      - const: rterm
68      - const: sel_t
69      - const: hs_i
70    description:
71      Should be the following names, which correspond to each nvmem-cells.
72      All of the 3 parameters associated with the above names are
73      required for each port, if any one is omitted, the trimming data
74      of the port will not be set at all.
75
76required:
77  - compatible
78  - reg
79  - "#phy-cells"
80  - clocks
81  - clock-names
82  - resets
83  - reset-names
84
85additionalProperties: false
86
87examples:
88  - |
89    usb-glue@65b00000 {
90        compatible = "socionext,uniphier-ld20-dwc3-glue", "simple-mfd";
91        #address-cells = <1>;
92        #size-cells = <1>;
93        ranges = <0 0x65b00000 0x400>;
94
95        usb_hsphy0: hs-phy@200 {
96            compatible = "socionext,uniphier-ld20-usb3-hsphy";
97            reg = <0x200 0x10>;
98            #phy-cells = <0>;
99            clock-names = "link", "phy";
100            clocks = <&sys_clk 14>, <&sys_clk 16>;
101            reset-names = "link", "phy";
102            resets = <&sys_rst 14>, <&sys_rst 16>;
103            vbus-supply = <&usb_vbus0>;
104            nvmem-cell-names = "rterm", "sel_t", "hs_i";
105            nvmem-cells = <&usb_rterm0>, <&usb_sel_t0>, <&usb_hs_i0>;
106        };
107    };
108