xref: /linux/Documentation/devicetree/bindings/phy/socionext,uniphier-pcie-phy.yaml (revision 1136fa0c07de570dc17858745af8be169d1440ba) 
1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/phy/socionext,uniphier-pcie-phy.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Socionext UniPhier PCIe PHY
8
9description: |
10  This describes the devicetree bindings for PHY interface built into
11  PCIe controller implemented on Socionext UniPhier SoCs.
12
13maintainers:
14  - Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
15
16properties:
17  compatible:
18    enum:
19      - socionext,uniphier-pro5-pcie-phy
20      - socionext,uniphier-ld20-pcie-phy
21      - socionext,uniphier-pxs3-pcie-phy
22      - socionext,uniphier-nx1-pcie-phy
23
24  reg:
25    maxItems: 1
26
27  "#phy-cells":
28    const: 0
29
30  clocks:
31    minItems: 1
32    maxItems: 2
33
34  clock-names:
35    oneOf:
36      - items:            # for Pro5
37          - const: gio
38          - const: link
39      - const: link       # for others
40
41  resets:
42    minItems: 1
43    maxItems: 2
44
45  reset-names:
46    oneOf:
47      - items:            # for Pro5
48          - const: gio
49          - const: link
50      - const: link       # for others
51
52  socionext,syscon:
53    $ref: /schemas/types.yaml#/definitions/phandle
54    description: A phandle to system control to set configurations for phy
55
56required:
57  - compatible
58  - reg
59  - "#phy-cells"
60  - clocks
61  - clock-names
62  - resets
63  - reset-names
64
65additionalProperties: false
66
67examples:
68  - |
69    pcie_phy: phy@66038000 {
70        compatible = "socionext,uniphier-ld20-pcie-phy";
71        reg = <0x66038000 0x4000>;
72        #phy-cells = <0>;
73        clock-names = "link";
74        clocks = <&sys_clk 24>;
75        reset-names = "link";
76        resets = <&sys_rst 24>;
77        socionext,syscon = <&soc_glue>;
78    };
79