1# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause 2%YAML 1.2 3--- 4$id: http://devicetree.org/schemas/phy/samsung,usb3-drd-phy.yaml# 5$schema: http://devicetree.org/meta-schemas/core.yaml# 6 7title: Samsung Exynos SoC USB 3.0 DRD PHY USB 2.0 PHY 8 9maintainers: 10 - Krzysztof Kozlowski <krzk@kernel.org> 11 - Marek Szyprowski <m.szyprowski@samsung.com> 12 - Sylwester Nawrocki <s.nawrocki@samsung.com> 13 14description: | 15 For samsung,exynos5250-usbdrd-phy and samsung,exynos5420-usbdrd-phy 16 compatible PHYs, the second cell in the PHY specifier identifies the 17 PHY id, which is interpreted as follows:: 18 0 - UTMI+ type phy, 19 1 - PIPE3 type phy. 20 21 For SoCs like Exynos5420 having multiple USB 3.0 DRD PHY controllers, 22 'usbdrd_phy' nodes should have numbered alias in the aliases node, in the 23 form of usbdrdphyN, N = 0, 1... (depending on number of controllers). 24 25properties: 26 compatible: 27 enum: 28 - google,gs101-usb31drd-phy 29 - samsung,exynos2200-usb32drd-phy 30 - samsung,exynos5250-usbdrd-phy 31 - samsung,exynos5420-usbdrd-phy 32 - samsung,exynos5433-usbdrd-phy 33 - samsung,exynos7-usbdrd-phy 34 - samsung,exynos7870-usbdrd-phy 35 - samsung,exynos850-usbdrd-phy 36 - samsung,exynos990-usbdrd-phy 37 - samsung,exynosautov920-usb31drd-combo-ssphy 38 - samsung,exynosautov920-usbdrd-combo-hsphy 39 - samsung,exynosautov920-usbdrd-phy 40 41 clocks: 42 minItems: 1 43 maxItems: 5 44 45 clock-names: 46 minItems: 1 47 maxItems: 5 48 description: | 49 Typically two clocks: 50 - Main PHY clock (same as USB DRD controller i.e. DWC3 IP clock), used 51 for register access. 52 - PHY reference clock (usually crystal clock), used for PHY operations, 53 associated by phy name. It is used to determine bit values for clock 54 settings register. For Exynos5420 this is given as 'sclk_usbphy30' 55 in the CMU. It's not needed for Exynos2200. 56 57 power-domains: 58 maxItems: 1 59 60 "#phy-cells": 61 const: 1 62 63 phys: 64 maxItems: 1 65 description: 66 USBDRD-underlying high-speed PHY 67 68 phy-names: 69 const: hs 70 71 port: 72 $ref: /schemas/graph.yaml#/properties/port 73 description: 74 Any connector to the data bus of this controller should be modelled using 75 the OF graph bindings specified. 76 77 reg: 78 minItems: 1 79 maxItems: 3 80 81 reg-names: 82 minItems: 1 83 items: 84 - const: phy 85 - const: pcs 86 - const: pma 87 88 samsung,pmu-syscon: 89 $ref: /schemas/types.yaml#/definitions/phandle 90 description: 91 Phandle to PMU system controller interface. 92 93 vbus-supply: 94 description: 95 VBUS power source. 96 97 vbus-boost-supply: 98 description: 99 VBUS Boost 5V power source. 100 101 pll-supply: 102 description: Power supply for the USB PLL. 103 104 dvdd-usb20-supply: 105 description: DVDD power supply for the USB 2.0 phy. 106 107 vddh-usb20-supply: 108 description: VDDh power supply for the USB 2.0 phy. 109 110 vdd33-usb20-supply: 111 description: 3.3V power supply for the USB 2.0 phy. 112 113 vdda-usbdp-supply: 114 description: VDDa power supply for the USB DP phy. 115 116 vddh-usbdp-supply: 117 description: VDDh power supply for the USB DP phy. 118 119 dvdd-supply: 120 description: 0.75V power supply for the USB phy. 121 122 vdd18-supply: 123 description: 1.8V power supply for the USB phy. 124 125 vdd33-supply: 126 description: 3.3V power supply for the USB phy. 127 128required: 129 - compatible 130 - clocks 131 - clock-names 132 - "#phy-cells" 133 - reg 134 - samsung,pmu-syscon 135 136allOf: 137 - if: 138 properties: 139 compatible: 140 contains: 141 const: google,gs101-usb31drd-phy 142 then: 143 allOf: 144 - $ref: /schemas/usb/usb-switch.yaml# 145 - $ref: /schemas/usb/usb-switch-ports.yaml# 146 147 properties: 148 clocks: 149 items: 150 - description: Gate of main PHY clock 151 - description: Gate of PHY reference clock 152 - description: Gate of control interface AXI clock 153 - description: Gate of control interface APB clock 154 - description: Gate of SCL APB clock 155 156 clock-names: 157 items: 158 - const: phy 159 - const: ref 160 - const: ctrl_aclk 161 - const: ctrl_pclk 162 - const: scl_pclk 163 164 reg: 165 minItems: 3 166 167 reg-names: 168 minItems: 3 169 170 required: 171 - reg-names 172 - orientation-switch 173 - port 174 - pll-supply 175 - dvdd-usb20-supply 176 - vddh-usb20-supply 177 - vdd33-usb20-supply 178 - vdda-usbdp-supply 179 - vddh-usbdp-supply 180 181 - if: 182 properties: 183 compatible: 184 contains: 185 enum: 186 - samsung,exynos2200-usb32drd-phy 187 then: 188 properties: 189 clocks: 190 maxItems: 1 191 clock-names: 192 items: 193 - const: phy 194 reg: 195 maxItems: 1 196 reg-names: 197 maxItems: 1 198 required: 199 - phys 200 - phy-names 201 202 - if: 203 properties: 204 compatible: 205 contains: 206 enum: 207 - samsung,exynos5433-usbdrd-phy 208 - samsung,exynos7-usbdrd-phy 209 then: 210 properties: 211 clocks: 212 minItems: 5 213 maxItems: 5 214 215 clock-names: 216 items: 217 - const: phy 218 - const: ref 219 - const: phy_utmi 220 - const: phy_pipe 221 - const: itp 222 223 reg: 224 maxItems: 1 225 226 reg-names: 227 maxItems: 1 228 229 - if: 230 properties: 231 compatible: 232 contains: 233 enum: 234 - samsung,exynos5250-usbdrd-phy 235 - samsung,exynos5420-usbdrd-phy 236 - samsung,exynos7870-usbdrd-phy 237 - samsung,exynos850-usbdrd-phy 238 - samsung,exynos990-usbdrd-phy 239 - samsung,exynosautov920-usb31drd-combo-ssphy 240 - samsung,exynosautov920-usbdrd-combo-hsphy 241 - samsung,exynosautov920-usbdrd-phy 242 then: 243 properties: 244 clocks: 245 minItems: 2 246 maxItems: 2 247 248 clock-names: 249 items: 250 - const: phy 251 - const: ref 252 253 reg: 254 maxItems: 1 255 256 reg-names: 257 maxItems: 1 258 259 - if: 260 properties: 261 compatible: 262 contains: 263 enum: 264 - samsung,exynosautov920-usb31drd-combo-ssphy 265 - samsung,exynosautov920-usbdrd-combo-hsphy 266 - samsung,exynosautov920-usbdrd-phy 267 then: 268 required: 269 - dvdd-supply 270 - vdd18-supply 271 272 else: 273 properties: 274 dvdd-supply: false 275 vdd18-supply: false 276 277 - if: 278 properties: 279 compatible: 280 contains: 281 enum: 282 - samsung,exynosautov920-usbdrd-combo-hsphy 283 - samsung,exynosautov920-usbdrd-phy 284 then: 285 required: 286 - vdd33-supply 287 288 else: 289 properties: 290 vdd33-supply: false 291 292unevaluatedProperties: false 293 294examples: 295 - | 296 #include <dt-bindings/clock/exynos5420.h> 297 298 phy@12100000 { 299 compatible = "samsung,exynos5420-usbdrd-phy"; 300 reg = <0x12100000 0x100>; 301 #phy-cells = <1>; 302 clocks = <&clock CLK_USBD300>, <&clock CLK_SCLK_USBPHY300>; 303 clock-names = "phy", "ref"; 304 samsung,pmu-syscon = <&pmu_system_controller>; 305 vbus-supply = <&usb300_vbus_reg>; 306 }; 307